TEXAS INSTRUMENTS SN74ALVC14 Technical data

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SN74ALVC14

HEX SCHMITT-TRIGGER INVERTER

SCES107E – JULY 1997 – REVISED AUGUST 1999

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages

description

This hex Schmitt-trigger inverter is designed for

2.3-V to 3.6-V VCC operation.
The SN74ALVC14 contains six independent

inverters and performs the Boolean function
Y = A.

The SN74ALVC14 is characterized for operation
from –40°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTAOUTPUT

Y

H L

L H

D, DGV, OR PW PACKAGE

(TOP VIEW)

1A
1Y
2A
2Y
3A
3Y

GND

1
2
3
4
5
6
7

14
13
12
11
10

V

CC

6A
6Y
5A
5Y
4A

9

4Y

8

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

1

1A

3

2A 2Y

5

3A 3Y

9

4A 4Y

11

5A 5Y

13

6A 6Y

logic diagram, each inverter (positive logic)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

2

1Y

4
6

8
10
12

YA

Copyright  1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN74ALVC14
HEX SCHMITT-TRIGGER INVERTER

SCES107E – JULY 1997 – REVISED AUGUST 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

MIN MAX UNIT

V
V
V

I

OH

I

OL

T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.3 3.6 V

CC

Input voltage 0 V

I

Output voltage 0 V

O

VCC = 2.3 V –12

High-level output current

Low-level output current

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

VCC = 2.7 V
VCC = 3 V –24
VCC = 2.3 V 12
VCC = 2.7 V
VCC = 3 V 24

CC
CC

–12

12

V
V

mA

mA

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Positi

es

d

V

threshold

N

es

d

V

threshold

Hyst

(

)

V

(V

T+

V

T

)

V

V

I

mA

(INPUT)

(OUTPUT)

PARAMETER

TEST CONDITIONS

UNIT

SN74ALVC14

HEX SCHMITT-TRIGGER INVERTER

SCES107E – JULY 1997 – REVISED AUGUST 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS V

V

T+

ve-going

hol

thr

V

T–

egative-going

thr

hol

∆V

T

eresis

V

– V

–

–

IOH = –100 µA 2.3 V to 3.6 V VCC–0.2
IOH = –6 mA 2.3 V 2

OH

V

OL

I

I

I

CC

∆I

CC

C

†

All typical values are at VCC = 3.3 V, TA = 25°C.

i

IOH = –12 mA

IOH = –24 mA 3 V 2
IOL = 100 µA 2.3 V to 3.6 V 0.2
IOL = 6 mA 2.3 V 0.4

= 12

OL

IOL = 24 mA 3 V 0.55
VI = VCC or GND 3.6 V ±5 µA
VI = VCC or GND, IO = 0 3.6 V 10 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
VI = VCC or GND 3.3 V 4 pF

CC

2.3 V 0.7 1.7

2.7 V 0.8 2
3 V 0.8 2

3.6 V 0.8 2

2.3 V 0.35 1.3

2.7 V 0.4 1.4
3 V 0.6 1.5

3.6 V 0.8 1.8

2.3 V 0.3 1

2.7 V 0.3 1.1
3 V 0.3 1.2

3.6 V 0.3 1.2

2.3 V 1.7

2.7 V 2.2
3 V 2.4

2.3 V 0.7

2.7 V 0.4

MIN TYP†MAX UNIT

V

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)

PARAMETER

t

pd

operating characteristics, T

C

Power dissipation capacitance per inverter CL = 0, f = 10 MHz 27 31 pF

pd

FROM

A

= 25°C

A

TO

Y

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VCC = 2.5 V

± 0.2 V

MIN MAX MIN MAX MIN MAX

1 3.7 3.9 1 3.4 ns

VCC = 2.7 V

VCC = 2.5 V VCC = 3.3 V

TYP TYP

VCC = 3.3 V

± 0.3 V

UNIT

3

SN74ALVC14
HEX SCHMITT-TRIGGER INVERTER

SCES107E – JULY 1997 – REVISED AUGUST 1999

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 30 pF

(see Note A)

500 Ω

500 Ω

S1

= 2.5 V ± 0.2 V

V

CC

2 × V

CC

Open

GND

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

GND

CC

LOAD CIRCUIT

Timing

Input

t

Data

Input

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

PLZ

F. t

PZL

G. t

PLH

VCC/2

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

and t

PHZ

and t

PZH

and t

PHL

VCC/2

t

su

are the same as t
are the same as ten.
are the same as tpd.

h

VCC/2

VCC/2 VCC/2

.

dis

t

PHL

V

0 V

V

0 V

V

0 V

V

V

CC

CC

CC

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

t

w

V

0 V

V

0 V

V

V

V

0 V

CC

CC

CC

OL

OH

VCC/2VCC/2

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

Figure 1. Load Circuit and Voltage Waveforms

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74ALVC14

HEX SCHMITT-TRIGGER INVERTER

SCES107E – JULY 1997 – REVISED AUGUST 1999

PARAMETER MEASUREMENT INFORMATION

V

= 2.7 V AND 3.3 V ± 0.3 V

CC

From Output

Under Test

CL = 50 pF

(see Note A)

Timing

Input

Data

Input

Input

t

PLH

Output

500 Ω

500 Ω

LOAD CIRCUIT

1.5 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

t

h

S1

t

PHL

6 V

GND

2.7 V

0 V

2.7 V

0 V

V

V

Open

2.7 V

0 V

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

w

1.5 V

1.5 V

Open

6 V

GND

1.5 V1.5 V

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

2.7 V

0 V

2.7 V

0 V

3 V

V

OL

V

OH

0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

F. t

G. t

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

dis

.

Figure 2. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

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