Texas Instruments SN74ALVC126D, SN74ALVC126DGVR, SN74ALVC126DR, SN74ALVC126NSR, SN74ALVC126PWR Datasheet
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JUL Y 1997 – REVISED FEBRUAR Y 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
description
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of
the driver.
The SN74ALVC126 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE A
Y
H H H
H LL
LXZ
logic symbol
†
EN
1
2
1A
1Y
3
4
5
2A
2Y
6
10
9
3A
3Y
8
13
12
4A
4Y
11
1OE
2OE
3OE
4OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
Copyright 1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
D, DGV, OR PW PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JUL Y 1997 – REVISED FEBRUAR Y 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
1OE
2
1A 1Y
3
4
2OE
5
2A 2Y
6
10
3OE
9
3A 3Y
8
13
4OE
12
4A 4Y
11
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JUL Y 1997 – REVISED FEBRUAR Y 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
Supply voltage 1.65 3.6 V
VCC = 1.65 V to 1.95 V 0.65 × V
CC
V
IH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
CC
V
IL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VCC = 2.7 V to 3.6 V 0.8
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
VCC = 1.65 V –4
p
VCC = 2.3 V –12
IOHHigh-level output current
VCC = 2.7 V –12
mA
VCC = 3 V –24
VCC = 1.65 V 4
p
VCC = 2.3 V 12
IOLLow-level output current
VCC = 2.7 V 12
mA
VCC = 3 V 24
∆t/∆v Input transition rise or fall rate 5 ns/V
T
A
Operating free-air temperature –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
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