TEXAS INSTRUMENTS SN74ALVC08 Technical data
www.ti.com
FEATURES
A + B
D, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
RGY PACKAGE
(TOP VIEW)
1 14
7 8
2
3
4
5
6
13
12
11
10
9
4B
4A
4Y
3B
3A
1B
1Y
2A
2B
2Y
1A
3Y
V
GND
CC
A
B
Y
• Operates From 1.65 V to 3.6 V
• Max tpdof 2.9 ns at 3.3 V
• ± 24-mA Output Drive at 3.3 V
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This quadruple 2-input positive-AND gate is designed
for 1.65-V to 3.6-V V
The device performs the Boolean function Y = A · B
or Y =
in positive logic.
operation.
CC
SN74ALVC08
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES101I – JULY 1997 – REVISED OCTOBER 2004
T
A
-40 ° C to 85 ° C
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ORDERING INFORMATION
PACKAGE
QFN - RGY Tape and reel SN74ALVC08RGYR VA08
SOIC - D ALVC08
SOP - NS Tape and reel SN74ALVC08NSR ALVC08
TSSOP - PW Tape and reel SN74ALVC08PWR VA08
TVSOP - DGV Tape and reel SN74ALVC08DGVR VA08
(1)
Tube SN74ALVC08D
Tape and reel SN74ALVC08DR
ORDERABLE PART NUMBER TOP-SIDE MARKING
FUNCTION TABLE
(each gate)
INPUTS
A B
H H H
L X L
X L L
OUTPUT
Y
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
Copyright © 1997–2004, Texas Instruments Incorporated
www.ti.com
SN74ALVC08
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES101I – JULY 1997 – REVISED OCTOBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
V
Supply voltage range -0.5 4.6 V
CC
V
Input voltage range
I
V
Output voltage range
O
I
Input clamp current VI< 0 -50 mA
IK
I
Output clamp current VO< 0 -50 mA
OK
I
Continuous output current ± 50 mA
O
Continuous current through V
θ
Package thermal impedance NS package
JA
T
Storage temperature range -65 150 ° C
stg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
(2)
(2) (3)
CC
(1)
MIN MAX UNIT
-0.5 4.6 V
-0.5 V
+ 0.5 V
CC
or GND ± 100 mA
D package
DGV package
PW package
RGY package
(4)
(4)
(4)
(4)
(5)
86
127
76 ° C/W
113
47
RECOMMENDED OPERATING CONDITIONS
(1)
MIN MAX UNIT
V
V
V
V
V
I
OH
I
OL
Supply voltage 1.65 3.6 V
CC
V
= 1.65 V to 1.95 V 0.65 × V
CC
High-level input voltage V
IH
Low-level input voltage V
IL
Input voltage 0 3.6 V
I
Output voltage 0 V
O
High-level output current mA
Low-level output current mA
= 2.3 V to 2.7 V 1.7 V
CC
V
= 2.7 V to 3.6 V 2
CC
V
= 1.65 V to 1.95 V 0.35 × V
CC
= 2.3 V to 2.7 V 0.7 V
CC
V
= 2.7 V to 3.6 V 0.8
CC
V
= 1.65 V -4
CC
V
= 2.3 V -12
CC
V
= 2.7 V -12
CC
V
= 3 V -24
CC
V
= 1.65 V 4
CC
V
= 2.3 V 12
CC
V
= 2.7 V 12
CC
V
= 3 V 24
CC
CC
∆ t/ ∆ v Input transition rise or fall rate 5 ns/V
T
(1) All unused inputs of the device must be held at V
Operating free-air temperature -40 85 ° C
A
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
CC
CC
V
2
www.ti.com
QUADRUPLE 2-INPUT POSITIVE-AND GATE
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
IOH= -100 µ A 1.65 V to 3.6 V V
IOH= -4 mA 1.65 V 1.2
IOH= -6 mA 2.3 V 2
V
OH
IOH= -12 mA 2.7 V 2.2
IOH= -24 mA 3 V 2
IOL= 100 µ A 1.65 V to 3.6 V 0.2
IOL= 4 mA 1.65 V 0.45
V
OL
I
I
I
CC
∆ I
CC
C
i
(1) All typical values are at V
IOL= 6 mA 2.3 V 0.4
IOL= 12 mA
IOL= 24 mA 3 V 0.55
VI= V
VI= V
One input at V
VI= V
or GND 3.6 V ± 5 µ A
CC
or GND, IO= 0 3.6 V 10 µ A
CC
- 0.6 V, Other inputs at V
CC
or GND 3.3 V 4.5 pF
CC
= 3.3 V, TA= 25 ° C.
CC
or GND 3 V to 3.6 V 750 µ A
CC
SN74ALVC08
SCES101I – JULY 1997 – REVISED OCTOBER 2004
CC
MIN TYP
- 0.2
CC
2.3 V 1.7 V
3 V 2.4
2.3 V 0.7
2.7 V 0.4
(1)
MAX UNIT
V
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
V
= 1.8 V V
PARAMETER UNIT
t
pd
FROM TO
(INPUT) (OUTPUT)
A or B Y 1.2 5.3 1 3.2 3 1.2 2.9 ns
CC
± 0.15 V ± 0.2 V ± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
= 2.5 V V
CC
V
= 2.7 V
CC
= 3.3 V
CC
OPERATING CHARACTERISTICS
TA= 25 ° C
V
= 1.8 V V
PARAMETER TEST CONDITIONS UNIT
C
Power dissipation capacitance per gate CL= 0, f = 10 MHz 24 25 26 pF
pd
CC
TYP TYP TYP
= 2.5 V V
CC
= 3.3 V
CC
3
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V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
OH
V
OL
t
h
t
su
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
Open
GND
R
L
R
L
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at V
LOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + V
∆
VOH − V
∆
0 V
V
I
0 V
0 V
t
w
V
I
V
I
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
V
LOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
0 V
V
I
V
M
t
PHL
V
M
V
M
V
I
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
M
V
M
t
PLH
V
LOAD
V
LOAD
/2
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
1 kΩ
500 Ω
500 Ω
500 Ω
V
CC
R
L
2 × V
CC
2 × V
CC
6 V
6 V
V
LOAD
C
L
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
∆
V
CC
V
CC
2.7 V
2.7 V
V
I
VCC/2
VCC/2
1.5 V
1.5 V
V
M
tr/t
f
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUT
SN74ALVC08
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES101I – JULY 1997 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
Figure 1. Load Circuit and Voltage Waveforms
4
PACKAGE OPTION ADDENDUM
www.ti.com
20-Mar-2008
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
SN74ALVC08D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
SN74ALVC08DE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
SN74ALVC08DG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
SN74ALVC08DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS &
no Sb/Br)
SN74ALVC08DGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS &
no Sb/Br)
SN74ALVC08DGVRG4 ACTIVE TVSOP DGV 14 2000 Green (RoHS &
no Sb/Br)
SN74ALVC08DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
SN74ALVC08DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
SN74ALVC08DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
SN74ALVC08IDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
SN74ALVC08NSR ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br)
SN74ALVC08NSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br)
SN74ALVC08NSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br)
SN74ALVC08PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br)
SN74ALVC08PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br)
SN74ALVC08PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br)
SN74ALVC08RGYR ACTIVE QFN RGY 14 1000 Green (RoHS &
no Sb/Br)
SN74ALVC08RGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
Addendum-Page 1
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