Texas Instruments SN74ALS996-1NT, SN74ALS996DW, SN74ALS996DWR, SN74ALS996NT, SN74ALS996NT3 Datasheet

SN54ALS996 . . . JT PACKAGE

SN74ALS996 . . . DW OR NT PACKAGE

(TOP VIEW)

SN54ALS996 . . . FK PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

1D
2D
3D
4D
5D
6D
7D

8D
EN
RD

CLK

GND

V

CC

1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
OE
T/C
CLR

NC – No internal connection

3212827

12 13

5
6
7
8
9
10
11

25
24
23
22
21
20
19

3Q
4Q
5Q
NC
6Q
7Q
8Q

4D
5D
6D

NC

7D
8D

EN

426

14 15 16 17 18

RD

CLK

GND

NC

CLR

T/C

OE

3D2D1D

NC

1Q

2Q

V

CC

SN54ALS996, SN74ALS996

8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES

SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995

Copyright  1995, Texas Instruments Incorporated

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• 3-State I/O-Type Read-Back Inputs

• Bus-Structured Pinout

• T/C Determines True or Complementary

Data at Q Outputs

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs

description

These 8-bit latches are designed specifically for
storing the contents of the input data bus and
providing the capability of reading back the stored
data onto the input data bus. The Q outputs are
designed with bus-driving capability.

The edge-triggered flip-flops enter the data on the
low-to-high transition of the clock (CLK) input
when the enable (EN

) input is low. Data can be
read back onto the data inputs by taking the read
(RD

) input low, in addition to having EN low . When

EN

is high, both the read-back and write modes

are disabled. Transitions on EN

should only be

made with CLK high to prevent false clocking.
The polarity of the Q outputs can be controlled by

the polarity (T/C

) input. When T/C is high, Q is the

same as is stored in the flip-flops. When T/C

is low,
the output data is inverted. The Q outputs can be
placed in the high-impedance state by taking the
output-enable (OE

) input high. OE does not affect
the internal operation of the register. Old data can
be retained or new data can be entered while the
outputs are off.

A low level at the clear (CLR

) input resets the
internal registers low. The clear function is
asynchronous and overrides all other register
functions.

The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum
I

OL

for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.

The SN54ALS996 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS996 is characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES

SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995

2–2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

11

CLK

2D

2

3D

3

4D

4

5D

5

6D

6

7D

7

8D

8

5Q

19

6Q

18

7Q

17

8Q

16

2Q

22

3Q

21

4Q

20

1Q

23

1D

1

1D

9

EN

2

10

RD

R

13

CLR

N3

14

T/C

EN4

15

OE

3,4

&

EN2

C1

≥ 1

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, JT, and NT packages.

logic diagram (positive logic)

To Seven Other Channels

15

23

OE

1Q

14

T/C

13

CLR

10

RD

1D

C1

R

9

EN

11

CLK

1

1D

Pin numbers shown are for the DW, JT, and NT packages.

SN54ALS996, SN74ALS996

8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES

SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995

2–3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing diagram

ÌÌ

ÌÌ

ÌÌ

(T/C = H)

CLR

D

EN

RD

Q

OE

Async

Clear

Write

Input Data

Output

CLK

Read-Back Data

Output Data

Read
Back

t

su

t

h

t

w

t

su

t

dis

t

dis

t

dis

t

p

t

h

†

t

en

t

en

t

en

†

This hold time ensures that the read-back circuit will not create a conflict on the input data bus.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage, V

CC

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, V

I

(OE, RD, EN, CLK, CLR, and T/C) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to D inputs and to disabled 3-state outputs 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: SN54ALS996 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ALS996 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.