SN74ALS994
10-BIT D-TYPE TRANSPARENT READ-BACK LATCH
SDAS237A – OCTOBER 1984 – REVISED JANUARY 1995
• 3-State I/O-Type Read-Back Inputs
• Bus-Structured Pinout
• True Logic Outputs
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
description
This 10-bit latch is designed specifically for storing
the contents of the input data bus and providing
the capability of reading back the stored data onto
the input data bus.
The ten latches are transparent D-type latches.
While the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs.
Read back is provided through the output-enable (OERB
the output of the data latches passes back onto the input data bus. When OERB
data latches is isolated from the D inputs. OERB
does not affect the internal operation of the latches; however ,
precautions should be taken to avoid a bus conflict.
The SN74ALS994 is characterized for operation from 0°C to 70°C.
logic symbol
†
) input. When OERB is taken low, the data present at
DW OR NT PACKAGE
(TOP VIEW)
OERB
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
1
2
3
4
5
6
7
8
9
10
11
12
is taken high, the output of the
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
LE
LE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
1
13
2
3
4
5
6
7
8
9
10
11
OERB
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EN2
C1
1D
2
23
22
21
20
19
18
17
16
15
14
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
2–1
SN74ALS994
10-BIT D-TYPE TRANSPARENT READ-BACK LATCH
SDAS237A – OCTOBER 1984 – REVISED JANUAR Y 1995
logic diagram (positive logic)
timing diagram
Data Bus
LE
OERB
OERB
1
13
LE
223
1D
To Nine Other Channels
Input Data Read Back Input Data
t
su
†
t
su
t
h
1D
C1
t
dis
1Q
t
pd
Q
†
This setup time ensures that the read-back circuit will not create a conflict on the input data bus.
t
pd
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Voltage applied to D inputs 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(OERB and LE) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
‡
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS994
IOHHigh-level output current
mA
IOLLow-level output current
mA
tsuSetup time
ns
V
V
D
V
V
V
V
Q
V
V
I
V
V
mA
I
V
V
V
A
I
V
V
V
mA
I
CC
mA
10-BIT D-TYPE TRANSPARENT READ-BACK LATCH
SDAS237A – OCTOBER 1984 – REVISED JANUARY 1995
recommended operating conditions
MIN NOM MAX UNIT
V
CC
V
IH
V
IL
t
w
t
h
T
A
†
This setup time ensures that the read-back circuit will not create a conflict on the input data bus.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
V
IK
OH
OL
I
IH
IL
I
O
CC
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current.
¶
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
p
p
Pulse duration, LE high 10 ns
p
Hold time, data after LE↓ 5 ns
Operating free-air temperature 0 70 °C
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
VCC = 4.5 V, II = –18 mA –1.2 V
All outputs VCC = 4.5 V to 5.5 V, IOH = – 0.4 mA VCC –2
VCC = 4.5 V, IOH = – 2.6 mA 2.4 3.2
= 4.5
CC
= 4.5
CC
= 5.5
CC
= 5.5 V,
CC
= 5.5 V,
CC
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
VCC = 5.5 V,
OERB high
¶
Q
OERB, LE
D inputs
OERB, LE
D inputs
OERB, LE
D inputs
§
§
Q –2.6
D –0.4
Q 24
D 8
Data before LE↓ 10
Data before OERB↓
IOL = 4 mA 0.25 0.4
IOL = 8 mA 0.35 0.5
IOL = 12 mA 0.25 0.4
IOL = 24 mA 0.35 0.5
VI = 7 V 0.1
VI = 5.5 V 0.1
= 2.7
I
= 0.4
I
Q outputs high 30 50
Q outputs low 52 82
†
10
–0.1
–0.1
20
20
µ
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–3
SN74ALS994
()
()
D
Q
ns
LE
Q
ns
OERB
D
ns
10-BIT D-TYPE TRANSPARENT READ-BACK LATCH
SDAS237A – OCTOBER 1984 – REVISED JANUAR Y 1995
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V,
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
‡
t
en
§
t
PZH
PHZ
or t
or t
dis
PZL
PLZ
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
ten = t
§
t
= t
dis
FROM
(INPUT)
TO
(OUTPUT)
CL = 50 pF,
TA = MIN to MAX
MIN MAX
3 14
4 18
6 21
8 27
4 21
2 16
UNIT
†
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN74ALS994
10-BIT D-TYPE TRANSPARENT READ-BACK LATCH
SDAS237A – OCTOBER 1984 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
7 V
S1
1 kΩ
Test
Point
C
L
500 Ω
From Output
Under Test
(see Note A)
C
L
Test
Point
1 kΩ
Timing
Input
Data
Input
Input
In-Phase
Output
Out-of-Phase
Output
(see Note B)
LOAD CIRCUIT FOR Q OUTPUTS
1.3 V
t
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.3 V 1.3 V
t
PLH
t
PHL
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
h
1.3 V1.3 V
1.3 V1.3 V
t
3.5 V
0.3 V
3.5 V
0.3 V
t
PHL
PLH
3.5 V
0.3 V
V
OH
V
OL
V
OH
V
OL
LOAD CIRCUIT FOR D OUTPUTS
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note C)
Waveform 2
S1 Open
(see Note C)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V 1.3 V
t
w
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V1.3 V
1.3 V
t
PHZ
1.3 V
VOLTAGE WAVEFORMS
t
PLZ
3.5 V
0.3 V
3.5 V
0.3 V
0.3 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
V
OH
[
0 V
NOTES: A. CL includes probe and jig capacitance.
B. When measuring propagation delay times of 3-state outputs, switch S1 is open.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–5
SN74ALS994
10-BIT D-TYPE TRANSPARENT READ-BACK LATCH
SDAS237A – OCTOBER 1984 – REVISED JANUAR Y 1995
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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