SN74ALS992
9-BIT D-TYPE TRANSPARENT READ-BACK LATCH
WITH 3-STATE OUTPUTS
SDAS028B – APRIL 1984 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• 3-State I/O-Type Read-Back Inputs
• Bus-Structured Pinout
• True Logic Outputs
• Designed With Nine Bits for Parity
Applications
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
description
This 9-bit latch is designed specifically for storing
the contents of the input data bus and providing
the capability of reading back the stored data onto
the input data bus. In addition, this device provides
a 3-state buffer-type output and is easily
implemented in parity applications.
The nine latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow
the data (D) inputs. The Q outputs are in the 3-state condition when the output-enable (OEQ
) input is high.
Read back is provided through the output-enable (OERB
) input. When OERB is taken low, the data present at
the output of the data latches is allowed to pass back onto the input data bus. When OERB
is taken high, the
output of the data latches is isolated from the D inputs. OERB
does not affect the internal operation of the latches;
however, precautions should be taken not to create a bus conflict.
The SN74ALS992 is characterized for operation from 0°C to 70°C.
logic symbol
†
C1
13
LE
2D
3
3D
4
4D
5
5D
6
6D
7
7D
8
8D
9
2
5Q
19
6Q
18
7Q
17
8Q
16
2Q
22
3Q
21
4Q
20
1Q
23
1D
2
1D
R
11
CLR
EN2
1
OERB
EN3
14
OEQ
3
9D
10
9Q
15
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OERB
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
OEQ
LE
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74ALS992
9-BIT D-TYPE TRANSPARENT READ-BACK LATCH
WITH 3-STATE OUTPUTS
SDAS028B – APRIL 1984 – REVISED JANUARY 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
To Eight Other Channels
1
13
2
23
OERB
LE
1D
1Q
14
OEQ
11
CLR
R
timing diagram
Data Bus
LE
OERB
Q
t
su
t
h
t
pd
t
dis
Input Data Read Back Input Data
t
pd
t
su
†
CLR
= H, OEQ = L
†
This setup time ensures that the read-back circuit will not create a conflict on the input data bus.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
(OERB, OEQ, CLR, and LE) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to D inputs and to disabled 3-state outputs 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN74ALS992
9-BIT D-TYPE TRANSPARENT READ-BACK LATCH
WITH 3-STATE OUTPUTS
SDAS028B – APRIL 1984 – REVISED JANUARY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
p
Q –2.6
IOHHigh-level output current
D –0.4
mA
p
Q 24
IOLLow-level output current
D 8
mA
LE high 10
twPulse duration
CLR low 10
ns
p
Data before LE↓ 10
tsuSetup time
Data before OERB↓ 10
ns
t
h
Hold time, data after LE↓ 5 ns
T
A
Operating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
All outputs VCC = 4.5 V to 5.5 V, IOH = – 0.4 mA VCC –2
V
OH
Q
VCC = 4.5 V, IOH = – 2.6 mA 2.4 3.2
V
IOL = 4 mA 0.25 0.4
D
V
CC
= 4.5
V
IOL = 8 mA 0.35 0.5
V
OL
IOL = 12 mA 0.25 0.4
V
Q
V
CC
= 4.5
V
IOL = 24 mA 0.35 0.5
I
OZH
Q VCC = 5.5 V, VO = 2.7 V 20 µA
I
OZL
Q VCC = 5.5 V, VO = 0.4 V –20 µA
D inputs
VI = 5.5 V 0.1
I
I
All others
V
CC
= 5.5
V
VI = 7 V 0.1
mA
D inputs
‡
20
I
IH
All others
V
CC
= 5.5 V,
V
I
= 2.7
V
20
µ
A
D inputs
‡
–0.1
I
IL
All others
V
CC
=
5.5 V
,
V
I
=
0.4 V
–0.1
mA
I
O
§
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
Outputs high 30 50
I
CC
V
CC
= 5.5 V,
Outputs low 50 80
mA
OERB high
Outputs disabled 35 55
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current.
§
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN74ALS992
9-BIT D-TYPE TRANSPARENT READ-BACK LATCH
WITH 3-STATE OUTPUTS
SDAS028B – APRIL 1984 – REVISED JANUARY 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
TA = MIN to MAX
†
UNIT
()
()
MIN MAX
t
PLH
3 14
t
PHL
D
Q
4 16
ns
t
PLH
6 20
t
PHL
LE
Q
8 25
ns
Q
6 20
t
PHL
CLR
D
8 26
ns
t
en
‡
4 21
t
dis
§
OERB
D
2 14
ns
t
en
‡
4 18
t
dis
§
OEQ
Q
1 14
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
ten = t
PZH
or t
PZL
§
t
dis
= t
PHZ
or t
PLZ
SN74ALS992
9-BIT D-TYPE TRANSPARENT READ-BACK LATCH
WITH 3-STATE OUTPUTS
SDAS028B – APRIL 1984 – REVISED JANUARY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT FOR Q OUTPUTS
From Output
Under Test
Test
Point
500 Ω
S1
C
L
(see Note A)
7 V
500 Ω
LOAD CIRCUIT FOR D OUTPUTS
From Output
Under Test
Test
Point
1 kΩ
S1
C
L
(see Note A)
7 V
1 kΩ
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
t
PHZ
t
PLZ
0.3 V
t
PZL
t
PZH
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note C)
Waveform 2
S1 Open
(see Note C)
[
0 V
V
OH
V
OL
[
3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
t
PHL
t
PLH
t
PLH
t
PHL
Input
Out-of-Phase
Output
(see Note B)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
3.5 V
0.3 V
V
OL
V
OH
V
OH
V
OL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. When measuring propagation delay times of 3-state outputs, switch S1 is open.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
Figure 1. Load Circuits and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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