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SN74ALS867ADW
Datasheet
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Texas Instruments SN74ALS867ADW, SN74ALS867ADWR, SN74ALS867ANT, SN74ALS869DW, SN74ALS869DWR Datasheet

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SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
• Fully Programmable With Synchronous
Counting and Loading
• SN74ALS867A and ′AS867 Have
Asynchronous Clear; SN74ALS869 and
′AS869 Have Synchronous Clear
• Fully Independent Clock Circuit
Simplifies Use
• Ripple-Carry Output for n-Bit Cascading
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
description
These synchronous, presettable, 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (ENP
, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple­clock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positive­going) edge of the clock waveform.
These counters are fully programmable; they may be preset to any number between 0 and 255. The load-input circuitry allows parallel loading of the cascaded counters. Because loading is synchronous, selecting the load mode disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
SN54AS867, SN54AS869 . . . JT PACKAGE SN74ALS867A, SN74ALS869, SN74AS867,
SN74AS869 . . . DW OR NT PACKAGE
SN54AS867, SN54AS869 . . . FK PACKAGE
B C D
E F
G
NC – No internal connection
(TOP VIEW)
S0
1
S1
2
A
3
B
4
C
5
D
6
E
7
F
8
G
9
H
10
ENT
11
GND
12
(TOP VIEW)
AS1S0
432128
5 6 7 8 9 10 11
12 13 14 15 16
H
ENT
GND
24 23 22 21 20 19 18 17 16 15 14 13
V
CC
27 26
17 18
RCO
V
CC
ENP Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
CLK RCO
ENP
CLK
Q
25 24 23 22 21 20 19
Q
A
H
Q Q Q NC Q Q Q
B C D
E F G
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Two count-enable (ENP in accomplishing this function. Both ENP by the levels of the select (S0, S1) inputs as shown in the function table. ENT
and ENT) inputs and a ripple-carry (RCO) output are instrumental
and ENT must be low to count. The direction of the count is determined
is fed forward to enable RCO. RCO thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting up (all outputs high). This low-level overflow-carry pulse can be used to enable successive cascaded stages. Transitions at ENP
and ENT are allowed regardless of the level of CLK. All inputs are diode clamped to minimize
transmission-line effects, thereby simplifying system design. These counters feature a fully independent clock circuit. With the exception of the asynchronous clear on the
SN74ALS867A and ′AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q outputs until clocking occurs. For the ′AS867 and ′AS869, any time ENP goes or remains high. For the SN74ALS867A and SN74ALS869, any time ENT
and/or ENT is taken high, RCO either
is taken high, RCO either goes or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
SN54AS867, SN54AS869 SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUAR Y 1995
description (continued)
The SN54AS867 and SN54AS869 are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALS867A, SN74ALS869, SN74AS867, and SN74AS869 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
S1
S0 FUNCTION
L L Clear
L H Count down H L Load H H Count up
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
logic symbols
†
SN74ALS867A
S0 S1
ENT ENP
CLK
S0 S1
ENT ENP CLK
1 2 11
23 14
3
A
4
B
5
C
6
D
7
E
8
F
9
G
10
H
1 2 11
23 14
3
A
4
B
5
C
6
D
7
E
8
F
9
G
10
H
CTRDIV 256
0 1 G4
G5
2,6D
0 1 G4
G5
2,6D
0
M
3
C6/1,4,5–/3,4,5+
0R
SN74ALS869
CTRDIV 256
0
M
3
C6/1,4,5–/3,4,5+
0,6R
1,4CT=0
3,4CT=255
1,4CT=0
3,4CT=255
13
22 21 20 19
18 17 16 15
13
22 21 20 19
18 17 16 15
RCO
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
RCO
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54AS867, SN54AS869 SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUAR Y 1995
logic symbols (continued)
S0 S1
ENT ENP CLK
S0 S1
ENT ENP CLK
†
′AS867
1 2 11
23 14
3
A
4
B
5
C
6
D
7
E
8
F
9
G
10
H
1 2 11
23 14
3
A
4
B
5
C
6
D
7
E
8
F
9
G
10
H
CTRDIV 256
0 1 G4
G5
2,6D
0 1 G4
G5
2,6D
0
M
3
C6/1,4,5–/3,4,5+
0R
′AS869
CTRDIV 256
0
M
3
C6/1,4,5–/3,4,5+
0,6R
1,4,5CT=0
3,4,5CT=255
1,4,5CT=0
3,4,5CT=255
13
22 21 20 19
18 17 16 15
13
22 21 20 19
18 17 16 15
RCO
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
RCO
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
CLK
S0 S1
ENP
A
B
C
14 1 2
23
3
4
5
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
SN74ALS867A, SN74ALS869
SN74ALS867A Only (asynchronous clear)
1D
C1
R
1D
C1
R
1D
C1
R
22
21
20
Q
A
Q
B
Q
C
ENT
1D
6
D
7
E
8
F
9
G
10
H
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
19
18
17
16
15
13
Q
D
Q
E
Q
F
Q
G
Q
H
RCO
11
Pin numbers shown are for the DW, JT, and NT packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54AS867, SN54AS869 SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUAR Y 1995
logic diagram (positive logic)
′AS867, ′AS869
1
S0
S1
ENT ENP
CLK
2
′AS867 Only (asynchronous clear)
11 23
13
RCO
14
22
Q
21
20
19
A
Q
B
Q
C
Q
D
3
A
4
B
5
C
6
D
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
7
E
8
F
9
G
10
H
Pin numbers shown are for the DW, JT, and NT packages.
18
Q
E
1D
C1
R
17
Q
F
1D
C1
R
16
Q
G
1D
C1
R
15
Q
H
1D
C1
R
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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