Texas Instruments SN74ALS845-1NT, SN74ALS845DW, SN74ALS845NT, SN74ALS845NT3 Datasheet
DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
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18
17
16
15
14
13
OE1
OE2
1D
2D
3D
4D
5D
6D
7D
8D
CLR
GND
V
CC
OE3
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
PRE
LE
SN74ALS845
8-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS233A – DECEMBER 1983 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• 3-State Buffer-Type Outputs Drive Bus
Lines Directly
• Bus-Structured Pinout
• Provides Extra Bus-Driving Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
• Buffered Control Inputs to Reduce
dc Loading Effects
• Power-Up High-Impedance State
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
description
This 8-bit latch features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable
for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true
data at its outputs.
Because the clear (CLR
) and preset (PRE) inputs are independent of the clock (CLK) input, taking CLR low
causes the eight Q outputs to go low. Taking PRE
low causes the eight Q outputs to go high. When both PRE
and CLR are taken low, the outputs follow the preset condition.
The buffered output-enable (OE1
, OE2, and OE3) inputs can be used to place the eight outputs in either a
normal logic state (high or low levels) or a high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without interface or pullup components.
The output enables do not affect the internal operation of the latches. Previously stored data can be retained
or new data can be entered while the outputs are in the high-impedance state.
The -1 version of the SN74ALS845 is identical to the standard version, except that the recommended maximum
I
OL
for the -1 version is increased to 48 mA.
The SN74ALS845 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
PRE CLR OE1 OE2 OE3 LE D
Q
L X L L L X X H
H LLLLXX L
HHLLLHL L
HHLLLHH H
HHLLLLL Q
0
XXXXHXX Z
XXXHXXX Z
XXHXXXX Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74ALS845
8-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS233A – DECEMBER 1983 – REVISED JANUAR Y 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
23
8
6D
9
7D
10
8D
1D
3
1D
6Q
17
7Q
16
8Q
15
1Q
22
4
2D
5
3D
6
4D
7
5D
2Q
21
3Q
20
4Q
19
5Q
18
S2
14
R
11
C1
13
LE
OE3
PRE
CLR
2
1
2
OE1
OE2
EN
&
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
To Seven Other Channels
2
1D
OE1
PRE
3
1
14
11
13
1Q
22
CLR
LE
S2
C1
1D
R
OE2
2
OE3
23
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