DW OR NT PACKAGE
(TOP VIEW)
1
2
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4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE1
OE2
1D
2D
3D
4D
5D
6D
7D
8D
CLR
GND
V
CC
OE3
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
PRE
LE
SN74ALS845
8-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS233A – DECEMBER 1983 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• 3-State Buffer-Type Outputs Drive Bus
Lines Directly
• Bus-Structured Pinout
• Provides Extra Bus-Driving Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
• Buffered Control Inputs to Reduce
dc Loading Effects
• Power-Up High-Impedance State
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
description
This 8-bit latch features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable
for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true
data at its outputs.
Because the clear (CLR
) and preset (PRE) inputs are independent of the clock (CLK) input, taking CLR low
causes the eight Q outputs to go low. Taking PRE
low causes the eight Q outputs to go high. When both PRE
and CLR are taken low, the outputs follow the preset condition.
The buffered output-enable (OE1
, OE2, and OE3) inputs can be used to place the eight outputs in either a
normal logic state (high or low levels) or a high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without interface or pullup components.
The output enables do not affect the internal operation of the latches. Previously stored data can be retained
or new data can be entered while the outputs are in the high-impedance state.
The -1 version of the SN74ALS845 is identical to the standard version, except that the recommended maximum
I
OL
for the -1 version is increased to 48 mA.
The SN74ALS845 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
PRE CLR OE1 OE2 OE3 LE D
Q
L X L L L X X H
H LLLLXX L
HHLLLHL L
HHLLLHH H
HHLLLLL Q
0
XXXXHXX Z
XXXHXXX Z
XXHXXXX Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74ALS845
8-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS233A – DECEMBER 1983 – REVISED JANUAR Y 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
23
8
6D
9
7D
10
8D
1D
3
1D
6Q
17
7Q
16
8Q
15
1Q
22
4
2D
5
3D
6
4D
7
5D
2Q
21
3Q
20
4Q
19
5Q
18
S2
14
R
11
C1
13
LE
OE3
PRE
CLR
2
1
2
OE1
OE2
EN
&
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
To Seven Other Channels
2
1D
OE1
PRE
3
1
14
11
13
1Q
22
CLR
LE
S2
C1
1D
R
OE2
2
OE3
23
SN74ALS845
8-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS233A – DECEMBER 1983 – REVISED JANUARY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
OH
High-level output current –2.6 mA
p
24
IOLLow-level output current
48
‡
mA
CLR or PRE low 35
twPulse duration
LE high 20
ns
t
su
Setup time, data before LE↓ 10 ns
t
h
Hold time, data after LE↓ 5 ns
T
A
Operating free-air temperature 0 70 °C
‡
Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP§MAX UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2
V
OH
VCC = 4.5 V, IOH = –2.6 mA 2.4 3.2
V
IOL = 12 mA 0.25 0.4
V
OL
VCC = 4.5 V
IOL = 24 mA 0.35 0.5
V
IOL = 48 mA
‡
0.35 0.5
I
OZH
VCC = 5.5 V, VO = 2.7 V 20 µA
I
OZL
VCC = 5.5 V, VO = 0.4 V –20 µA
I
I
VCC = 5.5 V, VI = 7 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 µA
I
IL
VCC = 5.5 V, VI = 0.4 V –0.1 mA
I
O
¶
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
Outputs high 21 36
I
CC
VCC = 5.5 V
Outputs low 41 67
mA
Outputs disabled 25 42
‡
Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V
§
All typical values are at VCC = 5 V, TA = 25°C.
¶
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN74ALS845
8-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS233A – DECEMBER 1983 – REVISED JANUAR Y 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω
,
R2 = 500 Ω,
TA = MIN to MAX
†
UNIT
MIN MAX
t
PLH
2 13
t
PHL
D
Q
4 18
ns
t
PLH
5 21
t
PHL
LE
Q
8 26
ns
t
PLH
PRE
6 22
t
PHL
CLR
Q
6 24
ns
t
PZH
3 16
t
PZL
OE
Q
5 18
ns
t
PHZ
1 11
t
PLZ
OE
Q
2 12
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN74ALS845
8-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS233A – DECEMBER 1983 – REVISED JANUARY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
t
PHZ
t
PLZ
t
PHL
t
PLH
0.3 V
t
PZL
t
PZH
t
PLH
t
PHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
C
L
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
V
OL
V
OH
V
OH
V
OL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
V
OH
V
OL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
V
CC
R
L
Test
Point
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
C
L
(see Note A)
R
L
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright 1998, Texas Instruments Incorporated
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