Texas Instruments SN74ALS843DW, SN74ALS843DWR, SN74ALS843NT Datasheet
DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
PRE
LE
SN74ALS843
9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS232A – DECEMBER 1983 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• 3-State Buffer-Type Outputs Drive Bus
Lines Directly
• Bus-Structured Pinout
• Provides Extra Bus-Driving Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
• Buffered Control Inputs to Reduce
dc Loading Effects
• Power-Up High-Impedance State
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
description
This 9-bit bus-interface D-type latch features
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers,
I/O ports, bidirectional bus drivers, and working registers.
The nine latches are transparent D-type latches with noninverting data (D) inputs.
A buffered output-enable (OE
) input places the nine outputs in either a normal logic state (high or low logic levels)
or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE
does not affect the internal operation of the latches. Previously stored data can be retained or new data can
be entered while the outputs are off.
The SN74ALS843 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
PRE CLR OE LE D
Q
L X L X X H
H LLXX L
HHLHL L
HHLHH H
HHLLX Q
0
XXHXX Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74ALS843
9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS232A – DECEMBER 1983 – REVISED JANUAR Y 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
EN
1
7
6D
8
7D
9
8D
10
9D
1D
2
1D
6Q
18
7Q
17
8Q
16
9Q
15
1Q
23
3
2D
4
3D
5
4D
6
5D
2Q
22
3Q
21
4Q
20
5Q
19
S2
14
R
11
C1
13
LE
OE
PRE
CLR
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1D
OE
PRE
2
1
14
11
13
1Q
23
CLR
LE
S
C1
1D
R
To Eight Other Channels
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