SN74ALS841, SN74AS841A . . . DW OR NT PACKAGE
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OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
LE
SN74ALS842 . . . DW OR NT PACKAGE
(TOP VIEW)
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OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
LE
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• 3-State Buffer-Type Outputs Drive Bus
Lines Directly
• Bus-Structured Pinout
• Provide Extra Bus-Driving Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
• Buffered Control Inputs to Reduce
dc Loading Effects
• Power-Up High-Impedance State
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
description
These 10-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The ten latches are transparent D-type latches.
The SN74ALS841 and SN74AS841A have
noninverting data (D) inputs. The SN74ALS842
has inverting D
inputs.
A buffered output-enable (OE
) input places the ten
outputs in either a normal logic state (high or low
logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive provide
the capability to drive bus lines without interface or
pullup components.
OE
does not affect the internal operation of the latches. Previously stored data can be retained or new data can
be entered while the outputs are off.
The SN74ALS841, SN74AS841A, and SN74ALS842 are characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
SN74ALS841, SN74AS841A
INPUTS
OUTPUT
OE LE D
Q
L H H H
L HL L
LLX Q
0
HXX Z
SN74ALS842
INPUTS
OUTPUT
OE LE D
Q
L H H L
L HL H
LLX Q
0
HXX Z
logic symbols
†
EN
1
7
6D
8
7D
9
8D
10
9D
1D
2
1D
6Q
18
7Q
17
8Q
16
9Q
15
1Q
23
3
2D
4
3D
5
4D
6
5D
2Q
22
3Q
21
4Q
20
5Q
19
OE
C1
13
LE
11
10D
10Q
14
SN74ALS841, SN74AS841A
EN
1
7
8
9
10
1D
2
6Q
18
7Q
17
8Q
16
9Q
15
1Q
23
3
4
5
6
2Q
22
3Q
21
4Q
20
5Q
19
OE
C1
13
LE
11
10Q
14
SN74ALS842
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagrams (positive logic)
1D
OE
2
1
13
1Q
23
LE
1D
To Nine Other Channels
C1
SN74ALS841, SN74AS841A
1D
OE
2
1
13
1Q
23
LE
1D
To Nine Other Channels
C1
SN74ALS842
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN74ALS841, SN74ALS842 0°C to 70°C. . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN74ALS841
SN74ALS842
UNIT
MIN NOM MAX
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
OH
High-level output current –2.6 mA
I
OL
Low-level output current 24 mA
t
w
Pulse duration, LE high 20 ns
t
su
Setup time, data before LE↓ 10 ns
t
h
Hold time, data after LE↓ 5 ns
T
A
Operating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
SN74ALS841
SN74ALS842
UNIT
MIN TYP†MAX
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2
V
OH
VCC = 4.5 V, IOH = –2.6 mA 2.4 3.2
V
IOL = 12 mA 0.25 0.4
V
OL
V
CC
= 4.5
V
IOL = 24 mA 0.35 0.5
V
I
OZH
VCC = 5.5 V, VO = 2.7 V 20 µA
I
OZL
VCC = 5.5 V, VO = 0.4 V –20 µA
I
I
VCC = 5.5 V, VI = 7 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 µA
I
IL
VCC = 5.5 V, VI = 0.4 V –0.1 mA
I
O
‡
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
Outputs high 19 30
SN74ALS841 VCC = 5.5 V
Outputs low 38 62
Outputs disabled 23 40
I
CC
Outputs high 20 35
mA
SN74ALS842 VCC = 5.5 V
Outputs low 48 74
Outputs disabled 27 44
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω
,
R2 = 500 Ω,
TA = MIN to MAX
†
UNIT
SN74ALS841
MIN MAX
t
PLH
2 13
t
PHL
D
Q
2 13
ns
t
PLH
7 21
t
PHL
LE
Q
8 26
ns
t
PZH
2 12
t
PZL
OE
Q
2 12
ns
t
PHZ
2 10
t
PLZ
OE
Q
2 12
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω
,
R2 = 500 Ω,
TA = MIN to MAX
†
UNIT
SN74ALS842
MIN MAX
t
PLH
4 18
t
PHL
D
Q
3 13
ns
t
PLH
8 27
t
PHL
LE
Q
6 20
ns
t
PZH
2 12
t
PZL
OE
Q
2 12
ns
t
PHZ
1 10
t
PLZ
OE
Q
2 12
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN74AS841A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN74AS841A
MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
OH
High-level output current –24 mA
I
OL
Low-level output current 48 mA
t
w
Pulse duration, LE high 4 ns
t
su
Setup time, data before LE↓ 2.5 ns
t
h
Hold time, data after LE↓ 2.5 ns
T
A
Operating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74AS841A
PARAMETER
TEST CONDITIONS
MIN TYP†MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC –2
V
OH
IOH = –15 mA 2.4 3.2
V
V
CC
=
4.5 V
IOH = –24 mA 2
V
OL
VCC = 4.5 V, IOL = 48 mA 0.35 0.5 V
I
OZH
VCC = 5.5 V, VO = 2.7 V 50 µA
I
OZL
VCC = 5.5 V, VO = 0.4 V –50 µA
I
I
VCC = 5.5 V, VI = 7 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 µA
I
IL
VCC = 5.5 V, VI = 0.4 V –0.5 mA
I
O
‡
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
Outputs high 36 60
I
CC
VCC = 5.5 V
Outputs low 58 94
mA
Outputs disabled 56 93
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω
,
R2 = 500 Ω,
TA = MIN to MAX
†
UNIT
SN74AS841A
MIN MAX
t
PLH
1 6.5
t
PHL
D
Q
1 10.5
ns
t
PLH
2 12
t
PHL
LE
Q
2 12
ns
t
PZH
2 14
t
PZL
OE
Q
2 16
ns
t
PHZ
1 8
t
PLZ
OE
Q
1 8
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
t
PHZ
t
PLZ
t
PHL
t
PLH
0.3 V
t
PZL
t
PZH
t
PLH
t
PHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
C
L
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
V
OL
V
OH
V
OH
V
OL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
V
OH
V
OL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
V
CC
R
L
Test
Point
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
C
L
(see Note A)
R
L
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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