Texas Instruments SN74ALS679DW, SN74ALS679N Datasheet
SN74ALS679
12-BIT ADDRESS COMPARATOR
SDAS003C – JUNE 1982 – REVISED JANUARY 1995
• 12-Bit Address Comparator With Enable
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (N) 300-mil DIPs
description
This 12-bit address comparator simplifies
addressing of memory boards and/or other
peripheral devices. The four P inputs are normally
hardwired with a preprogrammed address. An
internal decoder determines what input
information applied to the A inputs must be low or
DW OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
A8
A9
GND
V
CC
G
Y
P3
P2
P1
P0
A12
A1 1
A10
high to cause a low state at the Y output. For
example, a positive-logic bit combination of 0111
(decimal 7) at the P input determines that inputs A1 through A7 must be low and that inputs A8 through A12 must
be high to cause the output to go low. Equality of the address applied at the A inputs to the preprogrammed
address is indicated by the output being low.
This device features an enable (G
) input. When G is low, the device is enabled. When G is high, the device is
disabled and the output is high, regardless of the A and P inputs.
The SN74ALS679 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
G P3 P2 P1 P0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
L L L L L H H H H H H H H H H H H L
L L LLHLHHHHHHHH H H H L
LLLHLLLHHHHHHH H H H L
LL LHHLL LHHHHHH H H H L
LLHLLLLL LHHHHH H H H L
LLHLHLLLLLHHHHHHH L
LLHHLLLLLLLHHHH H H L
LLHHHLLLLLLLHHH H H L
LHLLLLLLLLLLLHHH H L
LHLLHLLLLLLLLLH H H L
LHLHLLLLLLLLLL L H H L
LHLHHLLLLLLLLL L L H L
LHHLLLLLLLLLLHHH L L
LHHLHLLLLLLLLLHH L L
LHHHLLLLLLLLLLL H L L
LHHHHLLLLLLLLLL L L L
L All other combinations H
H Any combination H
†
The three shaded rows of the function table show combinations that would normally not be used in address
comparator applications. The logic symbols above are not valid for these combinations in which P = 12, 13, and 14.
If symbols valid for all combinations are required, starting with the fourth exclusive-OR from the bottom, change P ≥ 9
to P = 9...11/13 . . . 15, P ≥ 10 to P = 10/11/14/15, and P ≥ 11 to P = 11/15.
OUTPUT
Y
†
†
†
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
SN74ALS679
12-BIT ADDRESS COMPARATOR
SDAS003C – JUNE 1982 – REVISED JANUARY 1995
logic symbol
†
[ADDRESS COMP]
[P assumed ≠ 12, 13, 14]
EN
0
3
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12
P
P ≥ 1
P ≥ 2
P ≥ 3
P ≥ 4
P ≥ 5
P ≥ 6
P ≥ 7
P ≥ 8
P ≥ 9
P ≥ 10
10
P ≥ 11
11
P ≥ 12
12
1
2
3
4
5
6
7
8
9
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
&
18
Y
P0
P1
P2
P3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
19
G
14
15
16
17
1
2
3
4
5
6
7
8
9
11
12
13
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
A1
2
A2
3
A3
4
A4
5
A5
SN74ALS679
12-BIT ADDRESS COMPARATOR
SDAS003C – JUNE 1982 – REVISED JANUARY 1995
A6
A7
A8
A9
A10
A11
A12
P0
P1
P2
P3
6
7
8
9
11
12
13
14
15
16
17
19
G
18
Y
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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