Texas Instruments SN74ALS667NT, SN74ALS667NT3, SN74ALS666DW, SN74ALS666DWR, SN74ALS666NT Datasheet
...
SN74ALS666, SN74ALS667
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
WITH 3-STATE OUTPUTS
SDAS227A – JUNE 1984 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• 3-State I/O-Type Read-Back Inputs
• Bus-Structured Pinout
• Choice of True or Inverting Logic
– SN74ALS666...True Outputs
– SN74ALS667...Inverted Outputs
• Preset and Clear Inputs
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
description
These 8-bit D-type transparent latches are
designed specifically for storing the contents of
the input data bus, plus reading back the stored
data onto the input data bus. In addition, they
provide a 3-state buffer-type output and are easily
utilized in bus-structured applications.
While the latch enable (LE) is high, the Q outputs
of the SN74ALS666 follow the data (D) inputs. The
Q
outputs of the SN74ALS667 provide the inverse
of the data applied to its D inputs. The Q or
Q
output of both devices is in the high-impedance
state if either output-enable (OE1
or OE2) input is
at a high logic level.
Read back is provided through the read-back
control (OERB
) input. When OERB is taken low,
the data present at the output of the data latches
passes back onto the input data bus. When OERB
is taken high, the output of the data latches is
isolated from the D inputs. OERB
does not affect
the internal operation of the latches; however,
caution should be exercised to avoid a bus
conflict.
The SN74ALS666 and SN74ALS667 are
characterized for operation from 0°C to 70°C.
SN74ALS666 ...DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OERB
OE1
1D
2D
3D
4D
5D
6D
7D
8D
CLR
GND
V
CC
OE2
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
PRE
LE
SN74ALS667 . . . DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OERB
OE1
1D
2D
3D
4D
5D
6D
7D
8D
CLR
GND
V
CC
OE2
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
PRE
LE
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74ALS666, SN74ALS667
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
WITH 3-STATE OUTPUTS
SDAS227A – JUNE 1984 – REVISED JANUAR Y 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbols
†
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
R
11
C1
13
LE
2D
4
3D
5
4D
6
5D
7
6D
8
7D
9
8D
10
3
18
17
16
15
21
20
19
22
1D
3
1D
S
14
EN3
1
23
2
2
&
EN2
OE1
OE2
OERB
PRE
CLR
SN74ALS667
R
11
C1
13
LE
2D
4
3D
5
4D
6
5D
7
6D
8
7D
9
8D
10
3
5Q
18
6Q
17
7Q
16
8Q
15
2Q
21
3Q
20
4Q
19
1Q
22
1D
3
1D
S
14
EN3
1
23
2
2
&
EN2
OE1
OE2
OERB
PRE
CLR
SN74ALS666
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN74ALS666, SN74ALS667
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
WITH 3-STATE OUTPUTS
SDAS227A – JUNE 1984 – REVISED JANUARY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagrams (positive logic)
S
1D
C1
R
To Seven Other Channels
2
23
1
14
11
13
3
22
OE1
OE2
OERB
PRE
CLR
LE
1D
1Q
SN74ALS666
S
1D
C1
R
To Seven Other Channels
2
23
1
14
11
13
3
22
OE1
OE2
OERB
PRE
CLR
LE
1D
1Q
SN74ALS667
SN74ALS666, SN74ALS667
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
WITH 3-STATE OUTPUTS
SDAS227A – JUNE 1984 – REVISED JANUAR Y 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing diagram
Input Data
t
dis
t
h
t
su
†
Read Back
Data Bus
LE
Q
OERB
Input Data
t
pd
t
su
t
pd
CLR = H, PRE = H, OE1 = L, OE2 = L.
†
This setup time ensures the read-back circuit does not create a conflict on the input data bus.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
(all inputs except D inputs) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to D inputs and to disabled 3-state outputs 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN74ALS666, SN74ALS667 0°C to 70°C. . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74ALS666
SN74ALS667
UNIT
MIN NOM MAX
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
p
Q –2.6
IOHHigh-level output current
D –0.4
mA
p
Q 24
IOLLow-level output current
D 8
mA
LE high 10
t
w
Pulse duration
CLR
low 10
ns
PRE low 10
p
Data before LE↓ 10
tsuSetup time
Data before OERB↓ 10
ns
t
h
Hold time, data after LE↓ 5 ns
T
A
Operating free-air temperature 0 70 °C
SN74ALS666, SN74ALS667
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
WITH 3-STATE OUTPUTS
SDAS227A – JUNE 1984 – REVISED JANUARY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
SN74ALS666
SN74ALS667
UNIT
MIN TYP†MAX
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
All outputs VCC = 4.5 V to 5.5 V, IOH = – 0.4 mA VCC –2
V
OH
Q or Q
VCC = 4.5 V, IOH = – 2.6 mA 2.4 3.2
V
p
IOL = 4 mA 0.25 0.4
D inputs
V
CC
= 4.5
V
IOL = 8 mA 0.35 0.5
V
OL
IOL = 12 mA 0.25 0.4
V
Q
or
Q
V
CC
= 4.5
V
IOL = 24 mA 0.35 0.5
I
OZH
Q or Q VCC = 5.5 V, VO = 2.7 V 20 µA
I
OZL
Q or Q VCC = 5.5 V, VO = 0.4 V –20 µA
D inputs
VI = 5.5 V 0.1
I
I
All others
V
CC
= 5.5
V
VI = 7 V 0.1
mA
D inputs
‡
20
I
IH
All others
V
CC
= 5.5 V,
V
I
= 2.7
V
20
µ
A
D inputs
‡
–0.1
I
IL
All others
V
CC
=
5.5 V
,
V
I
=
0.4 V
–0.1
mA
I
O
§
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
Q outputs high 25 50
SN74ALS666
VCC = 5.5 V,
Q outputs low 40 73
OERB high
Q outputs disabled 30 55
I
CC
Q outputs high 25 50
mA
SN74ALS667
V
CC
=
5.5 V
,
Q outputs low 45 79
OERB high
Q outputs disabled 30 60
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports (QA through QH), the parameters IIH and IIL include the off-state output current.
§
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN74ALS666, SN74ALS667
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
WITH 3-STATE OUTPUTS
SDAS227A – JUNE 1984 – REVISED JANUAR Y 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
FROM
TO
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
TA = MIN to MAX
†
PARAMETER
(INPUT)
(OUTPUT)
SN74ALS666
UNIT
MIN MAX
t
PLH
3 14
t
PHL
D
Q
4 18
ns
t
PLH
6 21
t
PHL
LE
Q
8 27
ns
Q
9 29
t
PHL
CLR
D
11 32
ns
t
PLH
Q
7 22
t
PHL
PRE
D
9 28
ns
OERB D
4 21
t
en
‡
OE1, OE2 Q
4 21
ns
OERB D
1 14
t
dis
§
OE1, OE2 Q
1 14
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
ten = t
PZH
or t
PZL
§
t
dis
= t
PHZ
or t
PLZ
switching characteristics (see Figure 1)
FROM
TO
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
TA = MIN to MAX
†
PARAMETER
(INPUT)
(OUTPUT)
SN74ALS667
UNIT
MIN MAX
t
PLH
6 20
t
PHL
D
Q
4 15
ns
t
PLH
9 28
t
PHL
LE
Q
7 22
ns
Q
7 24
t
PHL
CLR
D
8 26
ns
t
PLH
Q
8 25
t
PHL
PRE
D
9 28
ns
OERB D
4 21
t
en
‡
OE1, OE2 Q
4 21
ns
OERB D
1 14
t
dis
§
OE1, OE2 Q
1 14
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
ten = t
PZH
or t
PZL
§
t
dis
= t
PHZ
or t
PLZ
SN74ALS666, SN74ALS667
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
WITH 3-STATE OUTPUTS
SDAS227A – JUNE 1984 – REVISED JANUARY 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT FOR Q OR Q OUTPUTS
From Output
Under Test
Test
Point
500 Ω
S1
C
L
(see Note A)
500 Ω
LOAD CIRCUIT FOR D OUTPUTS
From Output
Under Test
Test
Point
1 kΩ
S1
C
L
(see Note A)
7 V
1 kΩ
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
t
PHZ
t
PLZ
0.3 V
t
PZL
t
PZH
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
V
OH
V
OL
[
3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
t
PHL
t
PLH
t
PLH
t
PHL
Input
Out-of-Phase
Output
(see Note D)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
3.5 V
0.3 V
V
OL
V
OH
V
OH
V
OL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
7 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is open.
Figure 1. Load Circuits and Voltage Waveforms
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