SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JUL Y 1996
D
3-State Bus Driving Inverting Outputs
D
Buffered Control Inputs
D
Package Options Include Plastic
Small-Outline (DW), Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) 300-mil DIPs
description
These octal D-type edge-triggered flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively lowimpedance loads. They are particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input,
the Q
outputs are set to the complement of the
logic states set up at the data (D) inputs. The
’ALS534A and SN74AS534 have inverted outputs, but otherwise are functionally equivalent to
the ’ALS374A and SN74AS374.
A buffered output-enable (OE
eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
) input places the
SN74ALS534A, SN74AS534 . . . DW OR N PACKAGE
SN54ALS534A ...J PACKAGE
(TOP VIEW)
OE
1
1Q
2
1D
3
2D
4
2Q
5
3Q
6
3D
7
4D
8
9
4Q
GND
SN54ALS534A . . . FK PACKAGE
10
(TOP VIEW)
1D1QOE
2D
2Q
3Q
3D
4D
3212019
4
5
6
7
8
910111213
4Q
GND
20
19
18
17
16
15
14
13
12
11
V
CLK
CC
5Q
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
18
17
16
15
14
5D 8Q
CC
8D
7D
7Q
6Q
6D
OE
does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are off.
The SN54ALS534A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS534A and SN74AS534 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
INPUTS
OE CLK D
L ↑ H L
L ↑ LH
LH or L X Q
H X X Z
OUTPUT
Q
0
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JUL Y 1996
1
11
3
4
7
8
13
14
17
18
†
EN
C1
1D
logic symbol
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
12
15
16
19
logic diagram (positive logic)
1
OE
11
CLK
12
2
1Q
5
2Q
6
3Q
9
4Q
5Q
2
1Q
5
2Q
6
3Q
9
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
3
4
7
8
13
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
6D
7D
8D
14
17
18
1D
1D
1D
C1
C1
C1
15
16
19
6Q
7Q
8Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
VOLV
V
V
I
V
V
V
mA
SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JUL Y 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54ALS534A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
SN74ALS534A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54ALS534A SN74ALS534A
MIN NOM MAX MIN NOM MAX
V
CC
V
IH
V
IL
I
OH
I
OL
f
clock
t
w
t
su
t
h
T
A
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.7 0.8 V
High-level output current –1 –2.6 mA
Low-level output current 12 24 mA
Clock frequency 0 30 0 35 MHz
Pulse duration, CLK high or low 16.5 14 ns
Setup time, data before CLK↑ 10 10 ns
Hold time, data after CLK↑ 0 0 ns
Operating free-air temperature –55 125 0 70 °C
†
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS534A SN74ALS534A
MIN TYP‡MAX MIN TYP‡MAX
V
IK
V
OH
I
OZH
I
OZL
I
I
I
IH
IL
I
O
I
CC
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
CLK, OE
D
§
VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2
= 4.5
CC
= 4.5
CC
VCC = 5.5 V, VO = 2.7 V 20 20 µA
VCC = 5.5 V, VO = 0.4 V –20 –20 µA
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
= 5.5 V,
CC
VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
VCC = 5.5 V
IOH = –1 mA 2.4 3.3
IOH = –2.6 mA 2.4 3.2
IOL = 12 mA 0.25 0.4 0.25 0.4
IOL = 24 mA 0.35 0.5
= 0.4
I
Outputs high 11 19 11 19
Outputs low 19 28 19 28
Outputs disabled 10 31 20 31
–0.1 –0.1
–0.2 –0.2
V
mA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ALS534A, SN74ALS534A, SN74AS534
CLK
A
Q
ns
OE
A
Q
ns
OE
A
Q
ns
UNIT
twPulse duration
ns
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JUL Y 1996
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PLZ
FROM
(INPUT)
TO
(OUTPUT)
ny
ny
ny
R1 = 500 Ω
R2 = 500 Ω,
TA = MIN to MAX
SN54ALS534A SN74ALS534A
MIN MAX MIN MAX
30 35 MHz
3 17 3 12
4 18 4 16
3 19 3 17
4 20 4 18
1 12 1 10
1 25 2 14
,
†
UNIT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Storage temperature rang, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN74AS534 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
A
recommended operating conditions
SN74AS534
MIN NOM MAX
V
CC
V
IH
V
IL
I
OH
I
OL
f
clock
t
su
t
h
T
A
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
High-level output current –15 mA
Low-level output current 48 mA
Clock frequency 0 125 MHz
CLK high 4
CLK low 3
Setup time, data before CLK↑ 2 ns
Hold time, data after CLK↑ 2 ns
Operating free-air temperature 0 70 °C
‡
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
V
V
I
V
5.5 V
V
0.4 V
mA
CLK
A
Q
ns
OE
A
Q
ns
OE
A
Q
ns
SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JUL Y 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74AS534
MIN TYP†MAX
V
IK
OH
V
OL
I
OZH
I
OZL
I
I
I
IH
IL
I
O
I
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
OE, CLK
D
‡
VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC –2
VCC = 4.5 V, IOH = –15 mA 2.4 3.3
VCC = 4.5 V, IOL = 48 mA 0.34 0.5 V
VCC = 5.5 V, VO = 2.7 V 50 µA
VCC = 5.5 V, VI = 0.4 V –50 µA
VCC = 5.5 V, VI = 7 V 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 µA
,
=
CC
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
VCC = 5.5 V
=
I
Outputs high 77 120
Outputs low 84 128
Outputs disabled 84 128
–0.5
–2
mA
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PLZ
FROM
(INPUT)
TO
(OUTPUT)
ny
ny
ny
R1 = 500 Ω
R2 = 500 Ω,
TA = MIN to MAX
,
UNIT
§
SN74AS534
MIN MAX
125 MHz
3 8
4 9
2 6
3 10
2 6
2 6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JUL Y 1996
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
V
CC
From Output
Under Test
(see Note A)
C
L
Test
Point
R
L
From Output
Under Test
C
(see Note A)
L
R
L
Test
Point
From Output
Under Test
(see Note A)
7 V
RL = R1 = R2
S1
R1
C
L
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V 1.3 V
t
w
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
t
PLH
t
PHL
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...