SN54ALS29821 . . . JT PACKAGE
SN74ALS29821 . . . DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
CLK
SN54ALS29821, SN74ALS29821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS145B – JANUARY 1986 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Functionally Equivalent to AMD’s AM29821
• Provide Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
• Outputs Have Undershoot-Protection
Circuitry
• Power-Up High-Impedance State
• Buffered Control Inputs Reduce
dc Loading Effects
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) and Ceramic (JT) 300-mil DIPs
description
These 10-bit edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for
implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input.
A buffered output-enable (OE
) input can place the ten outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. The outputs also are in the high-impedance state during power-up and
power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In
the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE
does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ALS29821 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS29821 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE CLK D
Q
L ↑ H H
L ↑ LL
LLX Q
0
HXX Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS29821, SN74ALS29821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS145B – JANUARY 1986 – REVISED JANUARY 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
6Q
18
7Q
17
8Q
16
9Q
15
10Q
14
7
6D
8
7D
9
8D
10
9D
EN
1
1Q
23
3
2D
4
3D
5
4D
6
5D
2Q
22
3Q
21
4Q
20
5Q
19
13
CLK
OE
11
10D
C1
1D
2
1D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1D
OE
2
1
13
1Q
23
CLK
1D
To Nine Other Channels
C1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54ALS29821 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS29821 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN54ALS29821, SN74ALS29821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS145B – JANUARY 1986 – REVISED JANUARY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54ALS29821 SN74ALS29821
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.75 5 5.25 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
I
OH
High-level output current –24 –24 mA
I
OL
Low-level output current 48 48 mA
t
w
Pulse duration, CLK high or low 7 7 ns
t
su
Setup time, data before CLK↑ 4 4 ns
t
h
Hold time, data after CLK↑ 2 2 ns
T
A
Operating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS29821 SN74ALS29821
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 4.75 V , II = –18 mA –1.2 –1.2 V
IOH = –15 mA 2.4 3.3 2.4 3.3
V
OH
V
CC
=
4.75 V
IOH = –24 mA 2 3.1 2 3.1
V
V
OL
VCC = 4.75 V , IOL = 48 mA 0.35 0.5 0.35 0.5 V
I
OZH
VCC = 5.25 V , VO = 2.4 V 50 20 µA
I
OZL
VCC = 5.25 V , VO = 0.4 V –50 –20 µA
I
I
VCC = 5.25 V , VI = 5.5 V 0.1 0.1 mA
I
IH
VCC = 5.25 V , VI = 2.7 V 20 20 µA
I
IL
VCC = 5.25 V , VI = 0.4 V –0.5 –0.2 mA
I
OS
‡
VCC = 5.25 V , VO = 0 –75 –250 –75 –250 mA
I
CC
VCC = 5.25 V , Outputs open 80 115 80 115 mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
SN54ALS29821, SN74ALS29821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS145B – JANUARY 1986 – REVISED JANUARY 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
FROM TO
VCC = MIN to MAX†,
TA = MIN to MAX
†
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN54ALS29821 SN74ALS29821
UNIT
MIN MAX MIN MAX
t
PLH
2 11.5 2 10
t
PHL
CLK
A
ny
Q
C
L
=
50 pF
2 11.5 2 10
ns
t
PLH
2 21 16
t
PHL
CLK
A
ny
Q
C
L
=
300 pF
2 21 16
ns
t
PZH
1 17 14
t
PZL
OE
A
ny
Q
C
L
= 50 p
F
1 17 14
ns
t
PZH
1 25 20
t
PZL
OE
A
ny
Q
C
L
=
300 pF
1 29.5 23
ns
t
PHZ
1 16 14
t
PLZ
OE
A
ny
Q
C
L
= 50 p
F
1 14 12
ns
t
PHZ
p
1 12 9
t
PLZ
OE
A
ny
Q
C
L
=
5 pF
1 11 9
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS29821, SN74ALS29821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS145B – JANUARY 1986 – REVISED JANUARY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT
R1
1 kΩ
All Diodes
1N916 or 1N3064
From Output
Under Test
Test Point
S2
C
L
(see Note A)
RL = 180 Ω
1.5 V
1.5 V
1.5 V
3 V
3 V
0
0
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing Input
Data Input
1.5 V
1.5 V
3 V
3 V
0
0
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V
1.5 V
t
PHL
t
PLH
t
PLH
t
PHL
Out-of-Phase
Output
1.5 V 1.5 V
1.5 V1.5 V
1.5 V 1.5 V
3 V
0
V
OL
V
OH
V
OH
V
OL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
PHZ
t
PLZ
0.5 V
t
PZL
t
PZH
1.5 V1.5 V
1.5 V
1.5 V
3 V
0
Output
Control
Waveform 1
(see Note B)
Waveform 2
(see Note B)
≈ 0
V
OH
V
OL
≈ 1.5 V
0.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
V
CC
S1
SWITCH POSITION TABLE
TEST S1 S2
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Closed
Closed
Open
Closed
Closed
Closed
Closed
Closed
Closed
Open
Closed
Closed
≈ 4.5 V
≈ 1.5 V
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr≤ 2.5 ns, tf≤ 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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