Texas Instruments SN74ALS280D, SN74ALS280DR, SN74ALS280N, SN74ALS280N3, SN74AS280D Datasheet
...
SN74ALS280, SN74AS280
A–I
9-BIT PARITY GENERATORS/CHECKERS
SDAS038C – DECEMBER 1982 – REVISED DECEMBER 1994
• Generate Either Odd or Even Parity for Nine
Data Lines
D OR N PACKAGE
(TOP VIEW)
• Cascadable for n-Bit Parity
G
NC
1
H
2
3
I
4
5
6
7
• Can Be Used to Upgrade Existing Systems
Using MSI Parity Circuits
• Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
description
These universal 9-bit parity generators/checkers
Σ EVEN
Σ ODD
GND
NC – No internal connection
utilize advanced Schottky high-performance
circuitry and feature odd (Σ ODD) and even (Σ EVEN) outputs to facilitate operation of either odd- or even-parity
applications. The word-length capability is easily expanded by cascading.
These devices can be used to upgrade the performance of most systems utilizing the SN74ALS180 and
SN74AS180 parity generators/checkers. Although the SN74ALS280 and SN74AS280 are implemented without
expander inputs, the corresponding function is provided by the availability of an input (I) at terminal 4 and the
absence of any internal connection at terminal 3. This permits the SN74ALS280 and SN74AS280 to be
substituted for the SN74ALS180 and SN74AS180 in existing designs to produce an identical function even if
the devices are mixed with existing SN74ALS180 and SN74AS180 devices.
All SN74AS280 inputs are buffered to lower the drive requirements.
The SN74ALS280 and SN74AS280 are characterized for operation from 0°C to 70°C.
14
13
12
11
10
V
CC
F
E
D
C
B
9
A
8
FUNCTION TABLE
NO. OF INPUTS
THAT ARE HIGH
0, 2, 4, 6, 8 H L
1, 3, 5, 7, 9 L H
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
8
A
9
B
10
C
11
D
12
E
13
F
1
G
2
H
4
I
OUTPUTS
Σ EVEN Σ ODD
2k
5
6
Σ EVEN
Σ ODD
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN74ALS280, SN74AS280
9-BIT PARITY GENERATORS/CHECKERS
SDAS038C – DECEMBER 1982 – REVISED DECEMBER 1994
logic diagram (positive logic)
8
A
9
B
10
C
11
D
12
E
13
F
5
Σ EVEN
6
Σ ODD
1
G
2
H
4
I
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN74ALS280 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS280, SN74AS280
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
VOLV
V
V
(
)
(
)
(INPUT)
(OUTPUT)
An
EVEN
ns
AnyΣ ODD
ns
9-BIT PARITY GENERATORS/CHECKERS
SDAS038C – DECEMBER 1982 – REVISED DECEMBER 1994
recommended operating conditions
SN74ALS280
MIN NOM MAX
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
High-level output current –2.6 mA
Low-level output current 24 mA
Operating free-air temperature 0 70 °C
SN74ALS280
MIN TYP†MAX
V
I
I
I
I
I
IK
OH
I
IH
IL
O
CC
‡
VCC = 4.5 V, II = –18 mA –1.5 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2
VCC = 4.5 V, IOH = –2.6 mA 2.4 3.3
= 4.5
CC
VCC = 5.5 V, VI = 7 V 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 µA
VCC = 5.5 V, VI = 0.4 V –0.1 mA
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
VCC = 5.5 V 10 16 mA
IOL = 12 mA 0.25 0.4
IOL = 24 mA 0.35 0.5
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
PARAMETER
t
PLH
t
PHL
t
PLH
t
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PHL
FROM
INPUT
y
TO
OUTPUT
Σ
RL = 500 Ω
TA = MIN to MAX
MIN MAX
,
SN74ALS280
3 20
3 20
3 20
4 22
§
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALS280, SN74AS280
UNIT
PARAMETER
TEST CONDITIONS
UNIT
(
)
(
)
(INPUT)
(OUTPUT)
An
EVEN
ns
AnyΣ ODD
ns
9-BIT PARITY GENERATORS/CHECKERS
SDAS038C – DECEMBER 1982 – REVISED DECEMBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN74AS280 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
†
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74AS280
MIN NOM MAX
V
V
V
I
I
T
CC
IH
IL
OH
OL
A
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
High-level output current –2 mA
Low-level output current 20 mA
Operating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74AS280
MIN TYP‡MAX
V
IK
V
OH
V
OL
I
I
I
IH
I
IL
§
I
O
I
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
CC
VCC = 4.5 V, II = –18 mA –1.5 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC –2 V
VCC = 4.5 V, IOL = 20 mA 0.35 0.5 V
VCC = 5.5 V, VI = 7 V 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 µA
VCC = 5.5 V, VI = 0.4 V –0.5 mA
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
VCC = 5.5 V 25 35 mA
switching characteristics (see Figure 1)
¶
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
FROM
INPUT
y
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TO
OUTPUT
Σ
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω
TA = MIN to MAX
,
SN74AS280
MIN MAX
3 12
3 11
3 12
3 11.5
¶
UNIT
9-BIT PARITY GENERATORS/CHECKERS
SDAS038C – DECEMBER 1982 – REVISED DECEMBER 1994
APPLICATION INFORMATION
SN74ALS280, SN74AS280
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
G
H
I
25-LINE
Σ EVEN
Σ ODD
Σ EVEN
Σ ODD
PARITY GENERATOR/CHECKER
H - Even
L = Odd
H - Odd
L = Even
PARITY GENERATOR/CHECKER
A
B
C
Σ ODD
D
E
F
G
H
I
A
B
Σ ODD
C
D
E
F
G
H
I
81-LINE
A
B
C
Σ EVEN
D
E
F
G
Σ ODD
H
I
H - Even
L = Odd
H - Odd
L = Even
A
B
C
Σ EVEN
D
E
F
G
Σ ODD
H
I
Three SN74ALS280/SN74AS280 devices can be
used to implement a 25-line parity generator/
checker.
As an alternative, the Σ ODD outputs of two or three
parity generators/checkers can be decoded with a
2-input (′AS86A or ′ALS86) exclusive-OR gate for
18- or 27-line parity applications.
A
B
C
Σ ODD
D
E
F
G
H
I
Longer word lengths can be implemented by cascading SN74ALS280/SN74AS280
devices. Parity can be generated for word lengths up to 81 bits.
To Other
SN74AS280s
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74ALS280, SN74AS280
9-BIT PARITY GENERATORS/CHECKERS
SDAS038C – DECEMBER 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
From Output
Under Test
(see Note A)
C
L
Test
Point
R
L
From Output
Under Test
(see Note A)
7 V
V
CC
S1
R
L
Test
Point
C
L
From Output
Under Test
(see Note A)
R1
C
L
RL = R1 = R2
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V 1.3 V
t
w
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
t
PLH
t
PHL
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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