Datasheet SN54ALS259J, SN74ALS259D, SN74ALS259DR, SN74ALS259N Datasheet (Texas Instruments)

SN54ALS259, SN74ALS259

8-BIT ADDRESSABLE LATCHES

SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994

Copyright  1994, Texas Instruments Incorporated

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• 8-Bit Parallel-Out Storage Register

Performs Serial-to-Parallel Conversion With
Storage

• Asynchronous Parallel Clear

• Active-High Decoder

• Enable/Disable Input Simplifies Expansion

• Expandable for n-Bit Applications

• Four Distinct Functional Modes

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs

description

These 8-bit addressable latches are designed for
general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional
devices capable of storing single-line data in eight
addressable latches and being a 1-of-8 decoder or
demultiplexer with active-high outputs.

Four distinct modes of operation are selectable by
controlling the clear (CLR

) and enable (G) inputs
as shown in the function table. In the
addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To
eliminate the possibility of entering erroneous data in the latches, G

should be held high (inactive) while the
address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the
level of the D input with all other outputs low. In the clear mode, all outputs are low and unaf fected by the address
and data inputs.

The SN54ALS259 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS259 is characterized for operation from 0°C to 70°C.

Function Tables

FUNCTION

INPUTS

OUTPUT OF

EACH

CLR G

ADDRESSED

LATCH

OTHER

OUTPUT

FUNCTION

H L D Q

iO

Addressable latch

H HQiOQ

iO

Memory
L LD L8-line demultiplexer
L H L L Clear

D = the level at the data input.
QiO = the level of Qi (i = Q, 1,...7 as appropriate) before the indicated
steady-state input conditions were established.

SN54ALS259 ...J PACKAGE

SN74ALS259 ...D OR N PACKAGE

(TOP VIEW)

3212019

910111213

4
5
6
7
8

18
17
16
15
14

G
D
NC
Q7
Q6

S2
Q0

NC

Q1
Q2

SN54ALS259 . . . FK PACKAGE

(TOP VIEW)

S1S0NC

Q4

Q5

CLR

Q3

GND

NC

NC – No internal connection

V

CC

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

S0
S1

S2
Q0
Q1
Q2
Q3

GND

V

CC

CLR
G
D
Q7
Q6
Q5
Q4

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN54ALS259, SN74ALS259
8-BIT ADDRESSABLE LATCHES

SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Function Tables (Continued)

LATCH SELECTION

SELECT INPUTS

LATCH

S2 S1 S0

ADDRESSED

L L L 0
L LH 1
LHL 2
LHH 3
HLL 4
HLH 5
HHL 6
HHH 7

logic symbol

†

8M

0
7

0

1

S0

2

S1

2

3

S2

G8

14

Z10

15

Z9

13

D

9, 0D

Q0

4

G

CLR

10, 0R
9, 1D

Q1

5

10, 1R
9, 2D

Q2

6

10, 2R
9, 3D

Q3

7

10, 3R
9, 4D

Q4

9

10, 4R
9, 5D

Q5

10

10, 5R
9, 6D

Q6

11

10, 6R
9, 7D

Q7

12

10, 7R

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

SN54ALS259, SN74ALS259

8-BIT ADDRESSABLE LATCHES

SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

14

13

1

2

3

15

12

11

10

9

7

6

5

4

G

D

S0

S1

S2

CLR

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Pin numbers shown are for the D, J, and N packages.

SN54ALS259, SN74ALS259
8-BIT ADDRESSABLE LATCHES

SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, V

CC

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, V

I

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: SN54ALS259 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ALS259 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

SN54ALS259 SN74ALS259

MIN NOM MAX MIN NOM MAX

UNIT

V

CC

Supply voltage 4.5 5 5.5 4.5 5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.7 0.8 V

I

OH

High-level output current –0.4 –0.4 mA

I

OL

Low-level output current 4 8 mA

G low 20 15

twPulse duration

CLR low 10 10

ns

p

Data before G↑ 20 15

tsuSetup time

Address before G↑ 20 15

ns

Data after G↑ 0 0

thHold time

Address after G↑ 0 0

ns

T

A

Operating free-air temperature –55 125 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54ALS259 SN74ALS259

PARAMETER

TEST CONDITIONS

MIN TYP‡MAX MIN TYP‡MAX

UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.5 –1.5 V

V

OH

VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2 V

IOL = 4 mA 0.25 0.4 0.25 0.4

V

OL

V

CC

= 4.5

V

IOL = 8 mA 0.35 0.5

V

I

I

VCC = 5.5 V, VI = 7 V 0.1 0.1 mA

I

IH

VCC = 5.5 V, VI = 2.7 V 20 20 µA

I

IL

VCC = 5.5 V, VI = 0.4 V –0.1 –0.1 mA

I

O

§

VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA

I

CC

VCC = 5.5 V 14 22 14 22 mA

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

SN54ALS259, SN74ALS259

8-BIT ADDRESSABLE LATCHES

SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics (see Figure 1)

PARAMETER

FROM

(

INPUT

)

TO

(

OUTPUT

)

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω

,

TA = MIN to MAX

†

UNIT

(INPUT)

(OUTPUT)

SN54ALS259 SN74ALS259

MIN MAX MIN MAX

t

PHL

CLR Any Q 2 15 2 12 ns

t

PLH

4 22 4 19

t

PHL

Data

Any Q

2 15 2 12

ns

t

PLH

4 26 4 22

t

PHL

Address

Any Q

2 15 2 12

ns

t

PLH

4 22 4 20

t

PHL

E

xecute

Any Q

2 16 2 13

ns

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

SN54ALS259, SN74ALS259
8-BIT ADDRESSABLE LATCHES

SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

t

PHZ

t

PLZ

t

PHL

t

PLH

0.3 V

t

PZL

t

PZH

t

PLH

t

PHL

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

From Output

Under Test

Test
Point

R1

S1

C

L

(see Note A)

7 V

1.3 V

1.3 V1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

t

h

t

su

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data

Input

1.3 V 1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

High-Level

Pulse

Low-Level

Pulse

t

w

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

Out-of-Phase

Output

(see Note C)

1.3 V 1.3 V

1.3 V1.3 V

1.3 V 1.3 V

1.3 V1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

V

OL

V

OH

V

OH

V

OL

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

[

0 V

V

OH

V

OL

[

3.5 V

In-Phase

Output

0.3 V

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

R2

V

CC

R

L

Test
Point

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

From Output

Under Test

Test
Point

C

L

(see Note A)

R

L

RL = R1 = R2

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated