Texas Instruments SN74ALS166D, SN74ALS166DR, SN74ALS166N Datasheet
SN74ALS166
OUTPUT
CLR
SH/LD
CLK INH
CLK
SER
Q
H
PARALLEL-LOAD 8-BIT SHIFT REGISTER
SDAS156C – APRIL 1982 – REVISED DECEMBER 1994
• Synchronous Load
• Direct Overriding Clear
• Parallel-to-Serial Conversion
• Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
description
The SN74ALS166 parallel-load 8-bit shift register
is compatible with most other TTL logic families.
D OR N PACKAGE
SER
A
B
C
D
CLK INH
CLK
GND
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
V
CC
SH/LD
H
Q
H
G
F
E
CLR
All inputs are buffered to lower the drive
requirements. Input clamping diodes minimize
switching transients and simplify system design.
These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on a monolithic chip.
They feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR
serial-in modes are established by the shift/load (SH/LD
) input. When high, SH/LD enables the serial data (SER)
) input. The parallel-in or
input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside)
data (A–H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading,
serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through
a two-input positive-NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding
either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the
system clock to be free running and the register can be stopped on command with the clock input. CLK INH
should be changed to the high level only when CLK is high. The buffered CLR
overrides all other inputs, including
CLK, and sets all flip-flops to zero.
The SN74ALS166 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
PARALLEL
A...H Q
L X X X X X L L L
H XLLX XQA0Q
H LL↑X a...h a bh
HHL↑HXHQAnQ
H HL↑LXLQAnQ
H X H ↑ X X Q
INTERNAL
OUTPUTS
Q
A
Q
A0
B0
B0
B
Q
H0
Gn
Gn
Q
H0
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN74ALS166
PARALLEL-LOAD 8-BIT SHIFT REGISTER
SDAS156C – APRIL 1982 – REVISED DECEMBER 1994
logic symbol
†
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
†
CLR
SH/LD
CLK INH
CLK
SER
9
15
6
7
1
2
A
3
B
4
C
5
D
10
E
11
F
12
G
14
H
SRG8
R
M1 [Shift]
M2 [Load]
≥1
1, 3D
2, 3D
2, 3D
C3/1
logic diagram (positive logic)
SER A B C D E F G H
1234510111214
SH/LD
15
13
Q
H
CLR
CLK
CLK INH
9
R
1A
C1
7
6
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
13
1A
1S
Q
C1
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Loading...