SN74ALS166
OUTPUT
CLR
SH/LD
CLK INH
CLK
SER
Q
H
PARALLEL-LOAD 8-BIT SHIFT REGISTER
SDAS156C – APRIL 1982 – REVISED DECEMBER 1994
• Synchronous Load
• Direct Overriding Clear
• Parallel-to-Serial Conversion
• Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
description
The SN74ALS166 parallel-load 8-bit shift register
is compatible with most other TTL logic families.
D OR N PACKAGE
SER
A
B
C
D
CLK INH
CLK
GND
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
V
CC
SH/LD
H
Q
H
G
F
E
CLR
All inputs are buffered to lower the drive
requirements. Input clamping diodes minimize
switching transients and simplify system design.
These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on a monolithic chip.
They feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR
serial-in modes are established by the shift/load (SH/LD
) input. When high, SH/LD enables the serial data (SER)
) input. The parallel-in or
input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside)
data (A–H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading,
serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through
a two-input positive-NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding
either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the
system clock to be free running and the register can be stopped on command with the clock input. CLK INH
should be changed to the high level only when CLK is high. The buffered CLR
overrides all other inputs, including
CLK, and sets all flip-flops to zero.
The SN74ALS166 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
PARALLEL
A...H Q
L X X X X X L L L
H XLLX XQA0Q
H LL↑X a...h a bh
HHL↑HXHQAnQ
H HL↑LXLQAnQ
H X H ↑ X X Q
INTERNAL
OUTPUTS
Q
A
Q
A0
B0
B0
B
Q
H0
Gn
Gn
Q
H0
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN74ALS166
PARALLEL-LOAD 8-BIT SHIFT REGISTER
SDAS156C – APRIL 1982 – REVISED DECEMBER 1994
logic symbol
†
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
†
CLR
SH/LD
CLK INH
CLK
SER
9
15
6
7
1
2
A
3
B
4
C
5
D
10
E
11
F
12
G
14
H
SRG8
R
M1 [Shift]
M2 [Load]
≥1
1, 3D
2, 3D
2, 3D
C3/1
logic diagram (positive logic)
SER A B C D E F G H
1234510111214
SH/LD
15
13
Q
H
CLR
CLK
CLK INH
9
R
1A
C1
7
6
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
13
1A
1S
Q
C1
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, shift, load, inhibit, and shift sequences
CLK
CLK INH
CLR
SER
SH/LD
A
B
SN74ALS166
PARALLEL-LOAD 8-BIT SHIFT REGISTER
SDAS156C – APRIL 1982 – REVISED DECEMBER 1994
H
L
H
L
H
L
H
H
H HHHH
Inhibit
LLL
Parallel
Inputs
C
D
E
F
G
H
Q
H
Serial Shift Serial Shift
Clear Load
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALS166
VOLV
V
V
CLK
Q
ns
PARALLEL-LOAD 8-BIT SHIFT REGISTER
SDAS156C – APRIL 1982 – REVISED DECEMBER 1994
recommended operating conditions
V
CC
V
IH
V
IL
I
OH
I
OL
f
clock
t
w
t
su
t
h
T
A
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
High-level output current –0.4 mA
Low-level output current 8 mA
Clock frequency 45 MHz
Pulse duration
Setup time before CLK↑
Hold time, data after CLK↑ 3 ns
Operating free-air temperature 0 70 °C
MIN NOM MAX UNIT
CLR low 9
CLK high
CLK low 10
SH/LD 16
Data
CLR inactive 11
10
ns
7
ns
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
V
OH
I
I
I
IH
I
IL
‡
I
O
I
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: With 4.5 V applied to SER and all other inputs, except the clock, grounded, ICC is measured after a clock transition from 0 V to 4.5 V .
CC
VCC = 4.5 V, II = –18 mA –1.5 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 V
= 4.5
CC
VCC = 5.5 V, VI = 7 V 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 µA
VCC = 5.5 V, VI = 0.4 V –0.1 mA
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
VCC = 5.5 V, See Note 1 14 24 mA
IOL = 4 mA 0.25 0.4
IOL = 8 mA 0.35 0.5
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V,
PARAMETER
f
max
t
PHL
t
PLH
t
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
¶
All typical values are at VCC = 5 V, TA = 25°C.
PHL
FROM
(INPUT)
CLR
TO
(OUTPUT)
Q
H
H
CL = 50 pF,
RL = 500 Ω
TA = MIN to MAX
MIN TYP¶MAX
,
§
45 MHz
4 9 14 ns
2 7 12
2 9 13
UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUT UNDER TEST
(see Note C)
(see Test Table)
NOTES: A. CL includes probe and jig capacitance.
CLR
CLK
(see Note E)
Data Input
Output Q
B. Propagation delay times (t
C. A clear pulse is applied prior to each test.
D. tn = bit time before clocking transition, t
E. The clock pulse has the following characteristics: t
F. All pulse generators have the following characteristics: ZO ≈ 50 Ω; tr = tf = 2 ns. Duty cycle = 50% when testing f
t
w(clear)
H
≤ 20 ns.
1.3 V 1.3 V
1.3 V 1.3 V 1.3 V 1.3 V
t
w(CLK)
t
PHL
RL = 500 Ω
and t
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
PARALLEL-LOAD 8-BIT SHIFT REGISTER
TEST TABLE FOR SYNCHRONOUS INPUTS
DATA INPUT
FOR TEST
H0 V
Serial Input
t
w(clear)
t
n
t
su
t
PLH
VOLTAGE WAVEFORMS
) are measured at t
= bit time after one clocking transition, and t
n+1
w(clock)
tn + 1 (see Note D)
t
h
1.3 V1.3 V
. Proper shifting of data is verified at t
n+1
≤ 20 ns and PRR = 1 MHz. The clear pulse has the following characteristics:
SN74ALS166
SDAS156C – APRIL 1982 – REVISED DECEMBER 1994
OUTPUT TESTED
(see Note B)
QH at tn +
QH at tn +
tn +
1
t
h
1.3 V
= bit time after eight clocking transitions.
1
1
3.5 V
0.3 V
3.5 V
0.3 V
3.5
0.3 V
V
OH
V
OL
with a functional test.
n+8
.
max
t
su
1.3 V
SH/LD
4.5 V
t
n
t
PHL
n+8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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