Texas Instruments SN74ALS165D, SN74ALS165DR, SN74ALS165N, SN74ALS165N3, SNJ54ALS165FK Datasheet
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SN54ALS165, SN74ALS165
PARALLEL-LOAD 8-BIT REGISTERS
SDAS157B – JUNE 1982 – REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Complementary Outputs
• Direct Overriding Load (Data) Inputs
• Gated Clock Inputs
• Parallel-to-Serial Data Conversion
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ′ALS165 are parallel-load 8-bit serial shift
registers that, when clocked, shift the data toward
serial (Q
H
and QH) outputs. Parallel-in access to
each stage is provided by eight individual direct
data (A–H) inputs that are enabled by a low level
at the shift/load (SH/LD
) input. The ′ALS165 have
a clock-inhibit function and complemented serial
outputs.
Clocking is accomplished by a low-to-high
transition of the clock (CLK) input while SH/LD
is
held high and the clock inhibit (CLK INH) input is
held low. The functions of CLK and CLK INH are
interchangeable. Since a low CLK and a
low-to-high transition of CLK INH also
accomplishes clocking, CLK INH should be
changed to the high level only while CLK is high.
Parallel loading is inhibited when SH/LD
is held
high. The parallel inputs to the register are
enabled while SH/LD
is low independently of the
levels of the CLK, CLK INH, or serial (SER) inputs.
The SN54ALS165 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS165 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
SH/LD
CLK CLK INH
FUNCTION
L X X Parallel load
H H X No change
H X H No change
H L ↑ Shift
†
H ↑ L Shift
†
†
Shift = content of each internal register shifts
toward serial outputs. Data at SER is shifted
into first register.
SN54ALS165 ...J PACKAGE
SN74ALS165 ...D OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
D
C
NC
B
A
E
F
NC
G
H
SN54ALS165 . . . FK PACKAGE
(TOP VIEW)
CLK
SH/LD
NC
SER
CLK INH
H
GND
NC
NC – No internal connection
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SH/LD
CLK
E
F
G
H
Q
H
GND
V
CC
CLK INH
D
C
B
A
SER
Q
H
Q
H
Q
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS165, SN74ALS165
PARALLEL-LOAD 8-BIT REGISTERS
SDAS157B – JUNE 1982 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
SRG8
C1 [LOAD]
1
15
CLK INH
2
CLK
14
D
2D
10
SER
1D
11
A
1D
12
B
13
C
3
E
4
F
5
G
1D
6
H
C2/
7
9
≥1
SH/LD
Q
H
Q
H
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7
Q
H
Q
H
11 12 13 14 3 4 5 6
ABCDEFGH
Pin numbers shown are for the D, J, and N packages.
SN54ALS165, SN74ALS165
PARALLEL-LOAD 8-BIT REGISTERS
SDAS157B – JUNE 1982 – REVISED DECEMBER 1994
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical shift, load, and inhibit sequences
Load
E
Q
H
H
G
C
F
Data
Inputs
D
SH/LD
SER
CLK INH
CLK
B
A
Q
H
L
L
H
L
H
L
H
H
H
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
H
Inhibit Serial Shift
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54ALS165 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS165 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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