SN74ALS164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER
SDAS159D – APRIL 1982 – REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• AND-Gated (Enable/Disable) Serial Inputs
• Fully Buffered Clock and Serial Inputs
• Direct Clear
• Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
description
This 8-bit parallel-out serial shift register features
AND-gated serial (A and B) inputs and an
asynchronous clear (CLR
) input. The gated serial
inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets
the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which
determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low,
provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition
of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.
The SN74ALS164A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
†
CLR CLK A B Q
A
QB...Q
H
L X X X L L L
H LXXQA0Q
B0QH0
H ↑ HHHQAnQ
Gn
H ↑ LXLQAnQ
Gn
H ↑ X L L Q
AnQGn
†
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state input conditions were
established.
H = high level (steady state), L = low level (steady state)
X = irrelevant (any input, including transitions)
↑ = transition from low to high level
QAn, QGn = the level of QA or QG before the most recent
↑ transition of the clock; indicates a 1-bit shift.
D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A
B
Q
A
Q
B
Q
C
Q
D
GND
V
CC
Q
H
Q
G
Q
F
Q
E
CLR
CLK
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74ALS164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER
SDAS159D – APRIL 1982 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
SRG8
R
9
8
CLK
C1/
1
A
3
2
B
CLR
4
&
1D
5
6
10
11
12
13
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
R
C1
1R
1S
R
C1
1R
1S
R
C1
1R
1S
R
C1
1R
1S
R
C1
1R
1S
R
C1
1R
1S
R
C1
1R
1S
R
C1
1R
1S
9
8
1
2
A
B
Serial Inputs
CLR
CLK
3 4 5 6 10 11 12 13
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SN74ALS164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER
SDAS159D – APRIL 1982 – REVISED DECEMBER 1994
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, shift, and clear sequences
CLK
A
B
CLR
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Clear Clear
Serial InputsOutputs
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN74ALS164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER
SDAS159D – APRIL 1982 – REVISED DECEMBER 1994
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
OH
High-level output current –0.4 mA
I
OL
Low-level output current 8 mA
f
clock
Clock frequency 50 MHz
CLK 10
twPulse duration
CLR low 16
ns
Data 6
t
su
S
etup time before
CLK↑
CLR inactive 8
ns
t
h
Hold time, data after CLK↑ 2 ns
T
A
Operating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.5 V
V
OH
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 V
IOL = 4 mA 0.25 0.4
VOLV
CC
=
4.5 V
IOL = 8 mA 0.35 0.5
V
I
I
VCC = 5.5 V, VI = 7 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 µA
I
IL
VCC = 5.5 V, VI = 0.4 V –0.1 mA
I
O
‡
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
I
CC
VCC = 5.5 V, See Note 1 14 24 mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: With 4.5 V applied to the serial input and all other inputs, except the CLK, grounded, ICC is measured after a clock transition from
0 to 4.5 V .
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω
,
TA = MIN to MAX
§
UNIT
MIN TYP¶MAX
f
max
50 75 MHz
t
PHL
CLR Any Q 6 15 20 ns
t
PLH
4 9 16
t
PHL
CLK
Any Q
5 11 17
ns
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
¶
All typical values are at VCC = 5 V, TA = 25°C.
SN74ALS164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER
SDAS159D – APRIL 1982 – REVISED DECEMBER 1994
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
t
PHZ
t
PLZ
t
PHL
t
PLH
0.3 V
t
PZL
t
PZH
t
PLH
t
PHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
C
L
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
V
OL
V
OH
V
OH
V
OL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
V
OH
V
OL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
V
CC
R
L
Test
Point
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
C
L
(see Note A)
R
L
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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