SN74ALS1640A, SN74ALS1645A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDAS246B – DECEMBER 1982 – REVISED FEBRUARY 1997
D
Bidirectional Bus Transceivers in
High-Density 20-Pin Packages
D
Lower-Power Versions of SN74ALS640B
and SN74ALS645A
D
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (N) 300-mil DIPs
description
These octal bus transceivers are designed for
asynchronous two-way communication between
data buses. These devices transmit data from the
DW OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
OE
B1
B2
B3
B4
B5
B6
B7
B8
CC
A bus to the B bus or from the B bus to the A bus,
depending on the level at the direction-control
(DIR) input. The output-enable (OE
) input can be used to disable the device so that the buses are effectively
isolated. The SN74ALS1640A features inverting logic, while the SN74ALS1645A features noninverting logic.
The SN74ALS1640A and SN74ALS1645A are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OE DIR SN74ALS1640A SN74ALS1645A
L L B data to A bus B data to A bus
L HA data to B bus A data to B bus
H X Isolation Isolation
OPERATION
logic symbols
19
OE
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
SN74ALS1640A
G3
3 EN1 [BA]
3 EN2 [AB]
18
17
16
15
14
13
12
11
B1
B2
B3
B4
B5
B6
B7
B8
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
19
1
2
3
4
5
6
7
8
9
SN74ALS1645A
G3
3 EN1 [BA]
3 EN2 [AB]
1
18
B1
2
17
16
15
14
13
12
11
B2
B3
B4
B5
B6
B7
B8
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN74ALS1640A, SN74ALS1645A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDAS246B – DECEMBER 1982 – REVISED FEBRUARY 1997
logic diagrams (positive logic)
SN74ALS1640A
19
OE
1
DIR
218
A1
To Seven Other Transceivers
B1
19
OE
1
DIR
218
A1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
: All inputs 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
SN74ALS1645A
B1
To Seven Other Transceivers
†
I/O ports 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 1): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which
use a trace length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
V
V
V
I
OH
I
OL
T
2
Supply voltage 4.5 5 5.5 V
CC
High-level input voltage 2 V
IH
Low-level input voltage 0.8 V
IL
High-level output current –15 mA
Low-level output current 16 mA
Operating free-air temperature 0 70 °C
A
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS1640A
SN74ALS1645A
MIN NOM MAX
UNIT
V
V
VOLV
4.5 V
V
I
V
V
mA
I
V
V
V
A
I
V
V
V
mA
I
mA
A or B
B
A
ns
OE
A
B
ns
OE
A
B
ns
SN74ALS1640A, SN74ALS1645A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDAS246B – DECEMBER 1982 – REVISED FEBRUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS1640A
PARAMETER TEST CONDITIONS
V
IK
V
OH
I
IH
IL
I
O
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports, the parameters IIH and IIL include the off-state output current.
§
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
Control inputs
A or B ports
Control inputs
A or B ports
Control inputs
A or B ports
§
SN74ALS1640A VCC = 5.5 V 18 32
SN74ALS1645A VCC = 5.5 V 25 38
‡
‡
VCC = 4.5 V, II = –18 mA –1.5 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2
= 4.5
CC
=
CC
= 5.5
CC
= 5.5 V,
CC
= 5.5 V,
CC
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
IOH = –3 mA 2.4 3.2
IOH = –15 mA 2
IOL = 8 mA 0.25 0.4
IOL = 16 mA 0.35 0.5
VI = 7 V 0.1
VI = 5.5 V 0.1
= 2.7
I
= 0.4
I
SN74ALS1645A
MIN TYP†MAX
20
20
–0.1
–0.1
UNIT
V
µ
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
¶
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
FROM
(INPUT)
TO
(OUTPUT)
or
or
or
R1 = 500 Ω
R2 = 500 Ω,
TA = MIN to MAX
SN74ALS1640A SN74ALS1645A
MIN MAX MIN MAX
4 15 2 13
2 10 2 13
5 20 8 25
5 22 8 25
2 10 2 12
5 13 3 18
,
¶
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALS1640A, SN74ALS1645A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDAS246B – DECEMBER 1982 – REVISED FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
From Output
Under Test
(see Note A)
C
L
Test
Point
R
L
From Output
(see Note A)
Under Test
C
7 V
V
CC
S1
R
L
Test
Point
L
From Output
Under Test
(see Note A)
R1
C
L
RL = R1 = R2
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V 1.3 V
t
w
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
t
PLH
t
PHL
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
4
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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