Datasheet SN54AS161J, SN74ALS163BD, SN74ALS163BDR, SN74ALS163BN, SN74ALS163BN3 Datasheet (Texas Instruments)
...
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
• Internal Look-Ahead Circuitry for Fast
Counting
• Carry Output for n-Bit Cascading
• Synchronous Counting
• Synchronously Programmable
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These synchronous, presettable, 4-bit decade
and binary counters feature an internal carry
look-ahead circuitry for application in high-speed
counting designs. The SN54ALS162B is a 4-bit
decade counter. The ′ALS161B, ′ALS163B,
′AS161, and ′AS163 are 4-bit binary counters.
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincidentally with each other
when instructed by the count-enable (ENP, ENT)
inputs and internal gating. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple-clock)
counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of
the clock input waveform.
These counters are fully programmable; they may
be preset to any number between 0 and 9 or 15.
Because presetting is synchronous, setting up a
low level at the load (LOAD
counter and causes the outputs to agree with the
setup data after the next clock pulse, regardless of
the levels of the enable inputs.
) input disables the
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,
SN54AS163 ...J PACKAGE
SN74ALS161B, SN74ALS163B, SN74AS161,
SN74AS163 ...D OR N PACKAGE
SN54AS163 . . . FK PACKAGE
A
B
NC
C
D
NC – No internal connection
(TOP VIEW)
CLR
1
CLK
2
A
3
B
4
C
5
D
6
ENP
7
GND
8
(TOP VIEW)
CLK
3212019
4
5
6
7
8
910111213
ENP
CLR
GND
NC
NC
16
15
14
13
12
11
10
9
CC
V
LOAD
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
RCO
18
17
16
15
14
ENT
Q
Q
NC
Q
Q
A
B
C
D
The clear function for the ′ALS161B and ′AS161 is asynchronous. A low level at the clear (CLR
four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD
for the SN54ALS162B, ′ALS163B, and ′AS163 is synchronous, and a low level at CLR
, or enable inputs. The clear function
sets all four of the flip-flop
) input sets all
outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The
active-low output of the gate used for decoding is connected to CLR
to synchronously clear the counter to
0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this
function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,
produces a high-level pulse while the count is maximum (9 or 15 with Q
high). The high-level overflow
A
ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed,
regardless of the level of CLK.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
description (continued)
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for
operation over the full military temperature range of – 55°C to 125°C. The SN74ALS161B, SN74ALS163B,
SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.
logic symbols
′ALS161B AND ′AS161 BINARY COUNTERS
1
CLR
ENT
ENP
CLK
9
10
7
2
3
A
4
B
5
C
6
D
LOAD
†
WITH DIRECT CLEAR
CTRDIV16
CT=0
M1
M2
G3
G4
1, 5D
3CT=15
C5/2,3,4+
[1]
[2]
[4]
[8]
LOAD
CLR
ENT
ENP
CLK
′ALS163B AND ′AS163 BINARY COUNTERS
WITH SYNCHRONOUS CLEAR
1
CLR
ENT
ENP
CLK
9
10
7
2
3
A
4
B
5
C
6
D
15
14
13
12
11
15
RCO
14
Q
A
13
Q
B
12
Q
C
11
Q
D
SN54ALS162B DECADE COUNTER
WITH SYNCHRONOUS CLEAR
1
9
10
7
2
3
A
4
B
5
C
6
D
CTRDIV10
5CT=0
M1
M2
G3
G4
C5/2,3,4+
1, 5D
LOAD
3CT=9
[1]
[2]
[4]
[8]
CTRDIV16
5CT=0
M1
M2
G3
G4
C5/2,3,4+
1, 5D
RCO
Q
A
Q
B
Q
C
Q
D
3CT=15
[1]
[2]
[4]
[8]
15
14
13
12
11
RCO
Q
A
Q
B
Q
C
Q
D
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
logic diagram (positive logic)
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
LOAD
ENT
ENP
CLR
CLK
9
10
7
1
2
3
A
SN54ALS162B
1D
1D
C1
C1
15
14
13
RCO
Q
A
Q
B
4
B
5
C
6
D
Pin numbers shown are for the J package.
12
C1
1D
C1
1D
Q
C
11
Q
D
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
logic diagram (positive logic)
CLR
LOAD
ENT
ENP
CLK
1
9
10
7
2
3
A
′ALS163B and ′AS163
1D
1D
C1
C1
15
14
13
RCO
Q
A
Q
B
4
B
5
C
6
D
Pin numbers shown are for the D, J, and N packages.
′ALS161B and ′AS161 synchronous binary counters are similar; however, CLR
is asynchronous.
1D
1D
C1
C1
12
11
Q
C
Q
D
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
typical clear, preset, count, and inhibit sequences
SN54ALS162B
The following sequence is illustrated below:
1. Clear outputs to zero (SN54ALS162B is synchronous)
2. Preset to BCD 7
3. Count to 8, 9, 0, 1, 2, and 3
4. Inhibit
CLR
LOAD
A
SDAS276 – DECEMBER 1994
Data
Inputs
Data
Outputs
CLK
ENP
ENT
Q
Q
Q
Q
RCO
B
C
D
A
B
C
D
90123
Count Inhibit
Sync
Clear
78
Preset
Async
Clear
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
typical clear, preset, count, and inhibit sequences
′ALS161B, ′AS161, ′ALS163B, and ′AS163
The following sequence is illustrated below:
1. Clear outputs to zero (′ALS161B and ′AS161 are asynchronous; ′ALS163B and ′AS163 are
synchronous.)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
Data
Inputs
Data
Outputs
CLK
ENP
ENT
Q
Q
Q
Q
RCO
B
C
D
A
B
C
D
14 15 0 1 2
Count Inhibit
Sync
Clear
12 13
Preset
Async
Clear
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
twPulse duration
ns
ENP, ENT
before CLK↑
SN54ALS162B, ′ALS163B
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54ALS161B, SN54ALS162B,
A
SN54ALS163B –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS161B, SN74ALS163B 0°C to 70°C. . . . . . . . . . . . . . . . .
recommended operating conditions
V
CC
V
IH
V
IL
I
OH
I
OL
f
clock
t
su
t
h
T
A
SN54ALS161B
SN54ALS162B
SN54ALS163B
MIN NOM MAX MIN NOM MAX
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.7 0.8 V
High-level output current –0.4 –0.4 mA
Low-level output current 4 8 mA
Clock frequency 0 22 0 40 MHz
CLR high or low 20 12.5
′ALS161B CLR low 20 15
A, B, C, D 50 15
LOAD 20 15
Setup time
Hold time, all synchronous inputs after CLK↑ 0 0 ns
Operating free-air temperature –55 125 0 70 °C
′ALS161B
SN54ALS162B, ′ALS163B
′ALS161B CLR inactive 10 10
′
CLR low 20 15
CLR high 20 10
25 15
20 15
SN74ALS161B
SN74ALS163B
UNIT
ns
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
V
V
4.5 V
V
(
)
(
)
(INPUT)
(OUTPUT)
CLK
RCO
ns
CLK
Any Q
ns
ENT
RCO
ns
t
CLR
ns
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS161B
PARAMETER TEST CONDITIONS
V
IK
V
OH
OL
I
I
I
IH
I
IL
‡
I
O
I
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
CC
VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2 V
=
CC
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
VCC = 5.5 V, VI = 0.4 V –0.2 –0.2 mA
VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
VCC = 5.5 V 12 21 12 21 mA
IOL = 4 mA 0.25 0.4 0.25 0.4
IOL = 8 mA 0.35 0.5
SN54ALS162B
SN54ALS163B
MIN TYP†MAX MIN TYP†MAX
switching characteristics (see Figure 3)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
PHL
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
FROM
INPUT
TO
OUTPUT
Any Q 8 27 8 24
RCO 11 32 11 23
RL = 500 Ω
TA = MIN to MAX
SN54ALS161B SN74ALS161B
MIN MAX MIN MAX
22 40 MHz
5 34 5 20
5 27 5 20
4 19 4 15
6 25 6 20
3 18 3 13
3 17 3 13
SN74ALS161B
SN74ALS163B
,
§
UNIT
UNIT
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
PARAMETER
UNIT
CLK
RCO
ns
CLK
Any Q
ns
ENT
RCO
ns
tw*
Pulse duration
ns
tsu*
ns
′AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
switching characteristics (see Figure 3)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
FROM
(INPUT) (OUTPUT)
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PHL
TO
RL = 500 Ω
TA = MIN to MAX
SN54ALS162B
SN54ALS163B
MIN MAX MIN MAX
35 40 MHz
5 25 5 20
5 25 5 20
4 18 4 15
6 25 6 20
3 16 3 13
3 16 3 13
SDAS276 – DECEMBER 1994
,
†
SN74ALS163B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54AS161, SN54AS163 –55°C to 125°C. . . . . . . . . . . . . . . . . .
A
SN74AS161, SN74AS163 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
SN54AS161
SN54AS163
MIN NOM MAX MIN NOM MAX
V
CC
V
IH
V
IL
I
OH
I
OL
f
clock
th* Hold time, all synchronous inputs after CLK↑ 2 0 ns
T
A
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
High-level output current –2 –2 mA
Low-level output current 20 20 mA
* Clock frequency 0 65 0 75 MHz
*
Setup time
*
before CLK↑
Operating free-air temperature –55 125 0 70 °C
CLR high or low 7.7 6.7
′AS161 CLR low 10 8
A, B, C, D 10 8
LOAD 10 8
ENP, ENT
′AS161
′
CLR inactive 10 8
CLR low 14 12
CLR high (inactive) 10 9
10 8
SN74AS161
SN74AS163
UNIT
‡
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
(
)
(
)
(INPUT)
(OUTPUT)
t
CLK
Any Q
ns
ENT
RCO
ns
t
CLR
ns
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS161
PARAMETER TEST CONDITIONS
V
IK
V
OH
V
OL
LOAD 0.3 0.3
I
I
I
IH
I
IL
I
O
I
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
ENT
All others 0.1 0.1
LOAD 60 60
ENT
All others 20 20
LOAD –1.5 –1.5
ENT
All others –0.5 –0.5
‡
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC –2 VCC –2 V
VCC = 4.5 V, IOL = 20 mA 0.25 0.5 0.25 0.5 V
VCC = 5.5 V, VI = 7 V
VCC = 5.5 V, VI = 2.7 V
VCC = 5.5 V, VI = 0.4 V
VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
VCC = 5.5 V 35 53 35 53 mA
SN54AS163
MIN TYP†MAX MIN TYP†MAX
0.2 0.2
40 40
–1 –1
SN74AS161
SN74AS163
UNIT
mA
µA
mA
switching characteristics (see Figure 3)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
PARAMETER
f
* 65 75 MHz
max
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
PHL
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
FROM
INPUT
CLK
RCO (with LOAD high) 1 8.5 1 8
RCO (with LOAD low) 3 17.5 3 16.5
TO
OUTPUT
RCO 2 14 2 12.5
Any Q 2 14 2 13
RCO 2 14 2 12.5
RL = 500 Ω
TA = MIN to MAX
SN54AS161 SN74AS161
MIN MAX MIN MAX
1 7.5 1 7
2 14 2 13
1.5 10 1.5 9
1 9.5 1 8.5
,
§
UNIT
ns
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
(
)
(
)
(INPUT)
(OUTPUT)
t
CLK
Any Q
ns
ENT
RCO
ns
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
switching characteristics (see Figure 3)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
PARAMETER
f
* 65 75 MHz
max
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
FROM
INPUT
CLK
RCO (with LOAD high) 1 8.5 1 8
RCO (with LOAD low) 3 17.5 3 16.5
TO
OUTPUT
RCO 2 14 2 12.5
RL = 500 Ω
TA = MIN to MAX
SN54AS163 SN74AS163
MIN MAX MIN MAX
1 7.5 1 7
2 14 2 13
1.5 10 1.5 9
1 9.5 1 8.5
,
†
UNIT
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
APPLICATION INFORMATION
n-bit synchronous counters
This application demonstrates how the ripple-mode carry circuit (see Figure 1) and the carry-look-ahead circuit
(see Figure 2) can be used to implement a high-speed n-bit counter. The SN54ALS162B counts in BCD. The
′ALS161B, ′AS161, ′ALS163B, and ′AS163 count in binary. When additional stages are added, the f
decreases in Figure 1, but remains unchanged in Figure 2.
Clear (L)
Count (H)
Disable (L)
Load (L)
Count (H)
Disable (L)
Clock
CLR
LOAD
ENT
ENP
CLK
CLR
LOAD
ENT
ENP
CLK
LSB
CTR
CT=0
M1
G3
3CT=MAX
G4
C5/T,3,4+
A
1,5D
B
C
D
CTR
CT=0
M1
G3
3CT=MAX
G4
C5/T,3,4+
A
1,5D
B
C
D
RCO
Q
Q
Q
Q
RCO
Q
Q
Q
Q
A
B
C
D
A
B
C
D
Clear (L)
Count (H)
Disable (L)
Clock
Load (L)
CLR
LOAD
ENT
ENP
CLK
A
B
C
D
CLR
LOAD
ENT
ENP
CLK
A
B
C
D
CT=0
M1
G3
G4
C5/T ,3,4+
1,5D
CT=0
M1
G3
G4
C5/T ,3,4+
1,5D
LSB
CTR
3CT=MAX
CTR
3CT=MAX
RCO
Q
Q
Q
Q
RCO
Q
Q
Q
Q
max
A
B
C
D
A
B
C
D
f
= 1/(CLK to RCO t
max
CLR
LOAD
ENT
ENP
CLK
A
B
C
D
CLR
LOAD
ENT
ENP
CLK
A
B
C
D
CT=0
M1
G3
G4
C5/T,3,4+
1,5D
CT=0
M1
G3
G4
C5/T,3,4+
1,5D
CTR
3CT=MAX
CTR
3CT=MAX
To More Significant Stages
) + (ENT to RCO t
PLH
PLH
RCO
Q
A
Q
B
Q
C
Q
D
RCO
Q
A
Q
B
Q
C
Q
D
) (N – 2) + (ENT tsu)f
CLR
LOAD
ENT
ENP
CLK
CLR
LOAD
ENT
ENP
CLK
CT=0
M1
G3
G4
C5/T ,3,4+
A
1,5D
B
C
D
CT=0
M1
G3
G4
C5/T ,3,4+
A
1,5D
B
C
D
To More Significant Stages
= 1/(CLK to RCO t
max
Figure 1. Ripple-Mode Carry Circuit Figure 2. Carry-Look-Ahead Circuit
CTR
3CT=MAX
CTR
3CT=MAX
) + (ENP tsu)
PLH
RCO
Q
Q
Q
Q
RCO
Q
Q
Q
Q
A
B
C
D
A
B
C
D
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
V
CC
S1
R
L
Test
Point
C
L
R
L
From Output
Under Test
C
(see Note A)
Test
Point
L
From Output
Under Test
(see Note A)
R1
C
L
RL = R1 = R2
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V 1.3 V
t
w
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
t
PLH
t
PHL
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 3. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
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