Boolean Function Generators
Parallel-to-Serial Converters
Data Source Selectors
• Input Clamping Diodes Simplify System
Design
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These data selectors/multiplexers provide full
binary decoding to select one-of-eight data
sources. The strobe (G
logic level to enable the inputs. A high level at the
strobe terminal forces the W output high and the
Y output low.
The SN54ALS151 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS151 and SN74AS151 are
characterized for operation from 0°C to 70°C.
) input must be at a low
SN74ALS151, SN74AS151 ...D OR N PACKAGE
SN54ALS151 ...J PACKAGE
(TOP VIEW)
D3
1
D2
2
D1
3
D0
4
Y
5
W
6
G
7
GND
SN54ALS151 . . . FK PACKAGE
8
(TOP VIEW)
D2D3NC
D1
D0
NC
3212019
4
5
6
7
Y
8
W
910111213
16
15
14
13
12
11
10
9
V
CC
V
D4
D5
D6
D7
A
B
C
D4
18
17
16
15
14
CC
D5
D6
NC
D7
A
NC – No internal connection
FUNCTION TABLE
INPUTS
SELECT
CBA
XXXHLH
LLL L D0D0
LLH L D1D1
LHL L D2D2
LHH L D3D3
HLL L D4D4
HLH L D5D5
HHL L D6D6
HHHLD7D7
H = high level, L = low level, X = irrelevant
D0, D1, . . . D7 = the level of the respective D input
STROBE
G
YW
B
GND
NC
C
G
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN54ALS151, SN74ALS151, SN74AS151
1-OF-8 DATA SELECTORS/MULTIPLEXERS
SDAS205A – APRIL 1982 – REVISED DECEMBER 1994
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
†
EN
0
2
0
1
2
3
4
5
6
7
MUX
G
0
7
D0
D1
D2
D3
D4
D5
D6
D7
7
G
11
A
10
B
9
C
4
3
2
1
15
14
13
12
logic diagram (positive logic)
7
G
4
D0
5
Y
6
W
3
D1
2
D2
1
Data
Inputs
Data
Select
(binary)
Pin numbers shown are for the D, J, and N packages.
D3
D4
D5
D6
D7
15
14
13
12
11
A
10
B
9
C
5
Y
6
W
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS151, SN74ALS151, SN74AS151
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
4.5 V
V
V
V
V
1-OF-8 DATA SELECTORS/MULTIPLEXERS
SDAS205A – APRIL 1982 – REVISED DECEMBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PHL
FROM
INPUT
ny
ny
TO
OUTPUT
RL = 500 Ω
TA = MIN to MAX
MINMAX
,
SN74AS151
4.514.5
4.515
412
412
310.5
311
26.5
14.5
4.514
311
1.56
310
§
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ALS151, SN74ALS151, SN74AS151
1-OF-8 DATA SELECTORS/MULTIPLEXERS
SDAS205A – APRIL 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
From Output
Under Test
(see Note A)
C
L
Test
Point
R
L
From Output
Under Test
C
(see Note A)
7 V
V
CC
S1
R
L
Test
Point
L
From Output
Under Test
(see Note A)
R1
C
L
RL = R1 = R2
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V1.3 V
t
w
1.3 V1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V1.3 V
t
PLH
t
PHL
1.3 V1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.