Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ′ALS139 are dual 2-line to 4-line
decoders/demultiplexers designed for use in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems, these devices can minimize the
effects of system decoding. When employed with
high-speed memories utilizing a fast-enable
circuit, the delay times of these decoders and the
enable time of the memory are usually less than
the typical access time of the memory . Therefore,
the effective system delay introduced by the
Schottky-clamped system decoder is negligible.
SN54ALS139 ...J PACKAGE
SN74ALS139 ...D OR N PACKAGE
SN54ALS139 . . . FK PACKAGE
1B
1Y0
NC
1Y1
1Y2
(TOP VIEW)
1G
1A
1B
1Y0
1Y1
1Y2
1Y3
GND
(TOP VIEW)
3 2 1 20 19
4
5
6
7
8
910111213
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
1A1GNC
V
CC
2G
2A
2B
2Y0
2Y1
2Y2
2Y3
9
CC
2G
V
2A
18
17
2B
16
NC
15
2Y0
14
2Y1
The ′ALS139 comprise two individual 2-line to
4-line decoders in a single package. The
active-low enable (G
) input can be used as a data
NC – No internal connection
1Y3
GND
NC
2Y3
2Y2
line in demultiplexing applications. These
decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its
driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line ringing and
simplify system design.
The SN54ALS139 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS139 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
ENABLE
G
HXXHHHH
LLLLHHH
L LHHLHH
L HLHHLH
L HHHHHL
SELECT
BAY0Y1Y2Y3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN54ALS139, SN74ALS139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SDAS204A – APRIL 1982 – REVISED DECEMBER 1994
X/Y
†
4
12
11
10
1Y0
5
1Y1
6
1Y2
7
1Y3
2Y0
2Y1
2Y2
9
2Y3
0
1
2
3
1A
1B
1G
2A
2B
2G
2
3
1
14
13
15
logic symbols (alternatives)
2
1A
3
1B
1
1G
14
2A
13
2B
15
2G
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
1
EN
logic diagram (positive logic)
1A
1B
1
2
3
15
Enable 1G
Select
Inputs
Enable 2G
DMUX
0
G
1
7
12
11
0
0
3
1
2
3
4
1Y0
5
1Y1
6
1Y2
1Y3
2Y0
2Y1
Data
Outputs
12
11
10
4
1Y0
5
1Y1
6
1Y2
7
1Y3
2Y0
2Y1
2Y2
9
2Y3
14
Select
Inputs
Pin numbers shown are for the D, J, and N packages.
2
2A
2B
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
2Y2
9
2Y3
SN54ALS139, SN74ALS139
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
(
)
(
)
(INPUT)
(OUTPUT)
A or B
Y
ns
G
Y
ns
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SDAS204A – APRIL 1982 – REVISED DECEMBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
FROM
INPUT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TO
OUTPUT
RL = 500 Ω
TA = MIN to MAX
SN54ALS139 SN74ALS139
MINMAXMINMAX
317314
317314
317314
318315
,
¶
UNIT
3
SN54ALS139, SN74ALS139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SDAS204A – APRIL 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
V
CC
R
L
From Output
Under Test
(see Note A)
C
L
Test
Point
R
L
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
7 V
RL = R1 = R2
S1
R1
C
L
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V1.3 V
t
w
1.3 V1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V1.3 V
t
PLH
t
PHL
1.3 V1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. T esting and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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