Texas Instruments SN74AHCT86D, SN74AHCT86DBLE, SN74AHCT86DBR, SN74AHCT86DGVR, SN74AHCT86DR Datasheet
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SN54AHCT86, SN74AHCT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS250J – OCTOBER 1995 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
description
The ’AHCT86 devices are quadruple 2-input
exclusive-OR gates. These devices perform the
Boolean function Y = A ⊕ B or Y = A
positive logic.
The SN54AHCT86 is characterized for operation
over the full military temperature range of –55°C
to 125°C.The SN74AHCT86 is characterized for
operation from –40°C to 85°C.
B + AB in
SN54AHCT86 ...J OR W PACKAGE
SN74AHCT86 . . . D, DB, DGV, N, OR PW PACKAGE
SN54AHCT86 . . . FK PACKAGE
1Y
NC
2A
NC
2B
NC – No internal connection
(TOP VIEW)
1A
1
1B
2
1Y
3
2A
4
2B
5
2Y
6
GND
7
(TOP VIEW)
1B1ANC
3212019
4
5
6
7
8
910111213
2Y
GND
14
13
12
11
10
NC
9
8
CC
V
3Y
V
4B
4A
4Y
3B
3A
3Y
4B
18
17
16
15
14
3A
CC
4A
NC
4Y
NC
3B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
(each gate)
INPUTS
A B
L L L
L HH
H LH
H H L
OUTPUT
Y
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54AHCT86, SN74AHCT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS250J – OCTOBER 1995 – REVISED JANUARY 2000
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
†
1A
1B
2A
2B
3A
3B
4A
4B
1
2
4
5
9
10
12
13
= 1
3
1Y
6
2Y
8
3Y
11
4Y
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative
logic symbols.
EXCLUSIVE OR
= 1
These are five equivalent exclusive-OR symbols valid for an SN74AHCT86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
= 2k 2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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