Texas Instruments SN74AHCT595D, SN74AHCT595DBR, SN74AHCT595DR, SN74AHCT595N, SN74AHCT595NSR Datasheet
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SN54AHCT595, SN74AHCT595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS374F – MAY 1997 – REVISED JANUAR Y 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
8-Bit Serial-In, Parallel-Out Shift
D
Shift Register Has Direct Clear
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
description
The ’AHCT595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
the shift and storage registers. The shift register
has a direct overriding clear (SRCLR
(SER) input, and serial outputs for cascading.
When the output-enable (OE) input is high, the
outputs are in the high-impedance state.
) input, serial
SN54AHCT595 ...J OR W PACKAGE
SN74AHCT595 . . . D, DB, N, OR PW PACKAGE
SN54AHCT595 . . . FK PACKAGE
Q
D
Q
E
NC
Q
F
Q
G
NC – No internal connection
(TOP VIEW)
Q
1
B
Q
2
C
Q
3
D
Q
4
E
5
Q
F
6
Q
G
7
Q
H
GND
8
(TOP VIEW)
CQB
Q
3 2 1 20 19
4
5
6
7
8
910111213
H
Q
NC
GND
NC
16
15
14
13
12
11
10
9
VCCQ
′
H
Q
V
CC
Q
A
SER
OE
RCLK
SRCLK
SRCLR
Q
H′
A
SER
18
OE
17
NC
16
RCLK
15
14
SRCLK
SRCLR
Both the shift register clock (RCLK) and storage register clock (SRCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
The SN54AHCT595 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT595 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54AHCT595, SN74AHCT595
FUNCTION
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS374F – MAY 1997 – REVISED JANUAR Y 2000
INPUTS
SER SRCLK SRCLR RCLK OE
X X X X H Outputs QA–QH are disabled.
X X X X L Outputs QA–QH are enabled.
X X L X X Shift register is cleared.
L ↑ H X X
H ↑ H X X
X ↓ H X X Shift-register state is not changed.
X XX↑ X Shift-register data is stored into the storage register.
X X X ↓ X Storage-register state is not changed.
FUNCTION TABLE
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
†
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
EN3
R
1D
C2
SRG8
C1/
2D
2D
15
3
3
Q
A
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
7
Q
H
9
Q
H′
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
13
OE
SER
12
10
11
14
RCLK
SRCLR
SRCLK
1D
R
C1
SN54AHCT595, SN74AHCT595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS374F – MAY 1997 – REVISED JANUAR Y 2000
Q
3D
C3
Q
15
Q
A
2D
R
2D
R
2D
R
2D
R
2D
R
2D
R
C2
C2
C2
C2
C2
C2
Q
Q
Q
Q
Q
Q
3D
3D
3D
3D
3D
3D
C3
C3
C3
C3
C3
C3
Q
Q
Q
Q
Q
Q
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
2D
C2
R
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Q
3D
C3
7
Q
Q
H
9
Q
H′
3
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