Datasheet SN74AHCT594D, SN74AHCT594DBR, SN74AHCT594DR, SN74AHCT594N, SN74AHCT594NSR Datasheet (Texas Instruments)
...
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417C – JUNE 1998 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance
Implanted CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
8-Bit Serial-In, Parallel-Out Shift
Registers With Storage
D
Independent Direct Overriding Clears
on Shift and Storage Registers
D
Independent Clocks for Both Shift and
Storage Registers
D
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
DIPs
description
The ’AHCT594 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Separate clocks and direct
overriding clear (SRCLR, RCLR) inputs are
provided on both the shift and storage registers.
A serial (Q
purposes.
) output is provided for cascading
H′
SN54AHCT594 ...J OR W PACKAGE
SN74AHCT594 . . . D, DB, N, OR PW PACKAGE
SN54AHCT594 . . . FK PACKAGE
Q
D
Q
E
NC
Q
F
Q
G
NC – No internal connection
(TOP VIEW)
Q
1
B
Q
2
C
Q
3
D
Q
4
E
5
Q
F
6
Q
G
7
Q
H
GND
8
(TOP VIEW)
CQB
Q
3212019
4
5
6
7
8
910111213
H
Q
NC
NC
GND
16
15
14
13
12
11
10
9
VCCQ
′
H
Q
V
CC
Q
A
SER
RCLR
RCLK
SRCLK
SRCLR
Q
H′
A
SER
18
RCLR
17
NC
16
RCLK
15
14
SRCLK
SRCLR
Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks
are connected together, the shift register always is one count pulse ahead of the storage register.
The SN54AHCT594 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT594 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
SN54AHCT594, SN74AHCT594
FUNCTION
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417C – JUNE 1998 – REVISED JANUARY 2000
INPUTS
SER SRCLK SRCLR RCLK RCLR
X X L X X Shift register is cleared.
L ↑ H X X
H ↑ H X X
L ↓ H X X Shift-register state is not changed.
X X X X L Storage register is cleared.
X XX↑ H Shift-register data is stored in the storage register.
X X X ↓ H Storage-register state is not changed.
FUNCTION TABLE
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
†
SER
13
12
10
11
14
RCLR
RCLK C2
SRCLR
SRCLK
R3
R
1D
SRG8
C1/
2D
2D
15
3
3
Q
A
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
7
Q
H
9
Q
H′
2
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logic diagram (positive logic)
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417C – JUNE 1998 – REVISED JANUARY 2000
RCLR
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14 15
1D
R
2D
R
2D
R
2D
R
Q
C1
Q
C2
Q
C2
Q
C2
R
3D
R
3D
R
3D
R
3D
Q
C3
Q
C3
Q
C3
Q
C3
Q
A
1
Q
B
2
Q
C
3
Q
D
2D
R
2D
R
2D
R
2D
R
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
C2
C2
C2
C2
Q
Q
Q
Q
R
3D
R
3D
R
3D
R
3D
Q
C3
Q
C3
Q
C3
Q
C3
4
Q
E
5
Q
F
6
Q
G
7
Q
H
9
Q
H′
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417C – JUNE 1998 – REVISED JANUARY 2000
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H’
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
V
4.5 V
V
V
4.5 V
V
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417C – JUNE 1998 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AHCT594 SN74AHCT594
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
V
O
I
OH
I
OL
Dt/D
T
A
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 5.5 0 5.5 V
Output voltage 0 V
High-level output current –8 –8 mA
Low-level output current 8 8 mA
v Input transition rise or fall rate 20 20 ns/V
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
CC
0 V
CC
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
OH
OL
I
I
I
CC
∆I
CC
C
i
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
‡
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
VI = VCC or GND, IO = 0 5.5 V 2 20 20
One input at 3.4 V ,
‡
Other inputs at VCC or GND
VI = VCC or GND 5 V 2 10 10 pF
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5.5 V 1.35 1.5 1.5 mA
TA = 25°C SN54AHCT594 SN74AHCT594
MIN TYP MAX MIN MAX MIN MAX
4.4 4.5 4.4 4.4
3.94 3.8 3.8
0.1 0.1 0.1
0.36 0.44 0.44
m
A
m
A
5
SN54AHCT594, SN74AHCT594
UNIT
twPulse duration
ns
PARAMETER
UNIT
f
MH
RCLK
Q
Q
C
pF
ns
SRCLK
Q
C
pF
ns
RCLK
Q
Q
C
50 pF
ns
SRCLK
Q
C
pF
ns
PARAMETER
UNIT
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417C – JUNE 1998 – REVISED JANUARY 2000
timing requirements over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C SN54AHCT594 SN74AHCT594
MIN MAX MIN MAX MIN MAX
RCLK or SRCLK high or low 5 5.5 5.5
RCLR or SRCLR low 5.2 5.5 5.5
SER before SRCLK↑ 3 3 3
SRCLK↑ before RCLK↑
t
Setup time
su
t
Hold time SER after SRCLK↑ 2 2 2 ns
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together , in which case the shift
register is one clock pulse ahead of the storage register.
SRCLR low before RCLK↑ 5 5 5
SRCLR high (inactive) before SRCLK↑ 2.9 3.3 3.3
RCLR high (inactive) before RCLK↑ 3.4 3.8 3.8
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
RCLR QA–Q
SRCLR Q
RCLR QA–Q
SRCLR Q
–
A
H
H′
H
H′
–
A
H
H′
H
H′
†
MIN TYP MAX MIN MAX MIN MAX
CL = 15 pF 135* 170* 115* 115
CL = 50 pF 120 140 95 95
p
= 15
L
p
= 15
L
CL = 15 pF 4.5* 7.6* 1* 8.2* 1 8.2 ns
CL = 15 pF 4.1* 7.1* 1* 7.6* 1 7.6 ns
p
=
L
p
= 50
L
CL = 50 pF 6.6 10 1 10.7 1 10.7 ns
CL = 50 pF 6 9.2 1 10.1 1 10.1 ns
5 5 5
ns
TA = 25°C SN54AHCT594 SN74AHCT594
3.3* 6.2* 1* 6.5* 1 6.5
3.7* 6.5* 1* 6.9* 1 6.9
3.7* 6.8* 1* 7.2* 1 7.2
4.1* 7.2* 1* 7.6* 1 7.6
4.9 7.8 1 8.3 1 8.3
5.8 8.9 1 9.7 1 9.7
5.5 8.6 1 9.1 1 9.1
6 9.2 1 10.1 1 10.1
z
noise characteristics, V
NOTE 4: Characteristics are for surface-mount packages only.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
= 5 V, CL = 50 pF, TA = 25°C (see Note 4)
CC
SN74AHCT594
MIN TYP MAX
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2 V
Low-level dynamic input voltage 0.8 V
OL
OL
OH
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1 V
–0.6 V
3.8 V
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417C – JUNE 1998 – REVISED JANUARY 2000
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 112 pF
pd
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Test
Point
C
L
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
= 5 V, TA = 25°C
CC
PARAMETER TEST CONDITIONS TYP UNIT
V
CC
Open
GND
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
1.5 V
t
h
Open
V
CC
GND
V
CC
From Output
Under Test
C
(see Note A)
3-STATE AND OPEN-DRAIN OUTPUTS
L
LOAD CIRCUIT FOR
RL = 1 kΩ
3 V
0 V
S1
Timing Input
Data Input
3 V
0 V
3 V
0 V
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
50% V
50% V
CC
CC
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
50% V
t
PLH
50% V
3 V
0 V
V
CC
V
V
CC
V
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
1.5 V 1.5 V1.5 V 1.5 V
t
PZL
50% V
CC
t
PZH
50% V
CC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
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7
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