Texas Instruments SN74AHCT374DBLE, SN74AHCT374DBR, SN74AHCT374DGVR, SN74AHCT374DW, SN74AHCT374DWR Datasheet
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SN54AHCT374, SN74AHCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS241J – OCTOBER 1995 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
description
The ’AHCT374 devices are octal edge-triggered
D-type flip-flops that feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. This device is
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
SN74AHCT374 . . . DB, DGV, DW, N, OR PW PACKAGE
SN54AHCT374 ...J OR W PACKAGE
(TOP VIEW)
OE
1
1Q
2
1D
3
2D
4
2Q
5
3Q
6
3D
7
4D
8
4Q
9
GND
SN54AHCT374 . . . FK PACKAGE
2D
2Q
3Q
3D
4D
10
(TOP VIEW)
1D1QOE
3212019
4
5
6
7
8
910111213
20
19
18
17
16
15
14
13
12
11
CC
V
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
8Q
18
17
16
15
14
CC
8D
7D
7Q
6Q
6D
On the positive transition of the clock (CLK) input,
the Q outputs are set to the logic levels of the data
4Q
GND
CLK
5Q
5D
(D) inputs.
A buffered output-enable (OE
) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and the increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE
should be tied to V
through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHCT374 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT374 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54AHCT374, SN74AHCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS241J – OCTOBER 1995 – REVISED JANUARY 2000
FUNCTION TABLE
(each flip-flop)
INPUTS
OE CLK D
L ↑ H H
L ↑ LL
L H or L X Q
H X X Z
OUTPUT
Q
0
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
11
3
4
7
8
13
14
17
18
EN
C1
1D
logic diagram (positive logic)
1
OE
11
CLK
12
15
16
19
2
1Q
5
2Q
6
3Q
9
4Q
5Q
6Q
7Q
8Q
3
1D
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C1
1D
2
1Q
UNIT
SN54AHCT374, SN74AHCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS241J – OCTOBER 1995 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AHCT374 SN74AHCT374
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
V
O
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 20 20 ns/V
T
A
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 5.5 0 5.5 V
Output voltage 0 V
High-level output current –8 –8 mA
Low-level output current 8 8 mA
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
CC
0 V
CC
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54AHCT374, SN74AHCT374
PARAMETER
TEST CONDITIONS
V
UNIT
V
4.5 V
V
V
4.5 V
V
UNIT
PARAMETER
UNIT
f
MH
CLKQC
pF
ns
OE
Q
C
15 pF
ns
OE
Q
C
15 pF
ns
CLKQC
pF
ns
OE
Q
C
pF
ns
OE
Q
C
pF
ns
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS241J – OCTOBER 1995 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
OH
OL
I
I
I
OZ
I
CC
∆I
CC
C
i
C
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
VO = VCC or GND, VI = VIH or V
VI = VCC or GND, IO = 0 5.5 V 4 40 40
One input at 3.4 V ,
†
Other inputs at VCC or GND
VI = VCC or GND 5 V 4 10 10 pF
VO = VCC or GND 5 V 9 pF
5.5 V ±0.25 ±2.5 ±2.5
IL
5.5 V 1.35 1.5 1.5 mA
TA = 25°C SN54AHCT374 SN74AHCT374
MIN TYP MAX MIN MAX MIN MAX
4.4 4.5 4.4 4.4
3.94 3.8 3.8
0.1 0.1 0.1
0.36 0.44 0.44
m
A
m
A
m
A
timing requirements over recommended operating free-air temperature range, V
CC
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54AHCT374 SN74AHCT374
MIN MAX MIN MAX MIN MAX
t
w
t
su
t
h
Pulse duration, CLK high or low 6.5 6.5 6.5 ns
Setup time, data before CLK↑
Hold time, data after CLK↑ 2.5 2.5 2.5 ns
2.5 2.5 2.5 ns
switching characteristics over recommended free-air temperature operating range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.
CL = 15 pF 90** 140** 80** 80
CL = 50 pF 85 130 75 75
p
= 15
L
p
=
L
p
=
L
p
= 50
L
p
= 50
L
p
= 50
L
CL = 50 pF 1*** 1 ns
TA = 25°C SN54AHCT374 SN74AHCT374
MIN TYP MAX MIN MAX MIN MAX
5.6** 9.4** 1** 10.5** 1 10.5
5.6** 9.4** 1** 10.5** 1 10.5
6.5** 10.2** 1** 11.5** 1 11.5
6.5** 10.2** 1** 11.5** 1 11.5
6.2** 10.2** 1** 11** 1 11
6.2** 10.2** 1** 11** 1 11
6.4 10.4 1 11.5 1 11.5
6.4 10.4 1 11.5 1 11.5
7.3 11.2 1 12.5 1 12.5
7.3 11.2 1 12.5 1 12.5
7 11.2 1 12 1 12
7 11.2 1 12 1 12
= 5 V ± 0.5 V
z
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
UNIT
SN54AHCT374, SN74AHCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS241J – OCTOBER 1995 – REVISED JANUARY 2000
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2 V
Low-level dynamic input voltage 0.8 V
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 27 pF
pd
= 5 V, CL = 50 pF, TA = 25°C (see Note 4)
CC
OL
OL
OH
= 5 V, T
CC
PARAMETER TEST CONDITIONS TYP UNIT
= 25°C
A
SN74AHCT374
MIN TYP MAX
0.8 1.2 V
–0.8 –1.2 V
3.8 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54AHCT374, SN74AHCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS241J – OCTOBER 1995 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
V
CC
GND
Open
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
50% V
t
PHL
50% V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3-STATE AND OPEN-DRAIN OUTPUTS
CC
CC
LOAD CIRCUIT FOR
3 V
0 V
3 V
0 V
t
PHL
V
t
PLH
CC
CC
OH
V
OL
V
OH
V
OL
50% V
50% V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
1.5 V
t
CC
CC
h
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V1.5 V 1.5 V
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
3 V
0 V
3 V
0 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 2000, Texas Instruments Incorporated
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