TEXAS INSTRUMENTS SN74AHCT32-Q1 Technical data

OUTPUT

SN74AHCT32-Q1

QUADRUPLE 2-INPUT POSITIVE-OR GATE

SCLS528A − AUGUST 2003 − REVISED APRIL 2008

D Qualified for Automotive Applications

D ESD Protection Exceeds 1000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D EPIC (Enhanced-Performance Implanted

CMOS) Process

D Inputs Are TTL-Voltage Compatible

description/ordering information

The SN74AHCT32 is a quadruple 2-input
positive-OR gate. This device performs the Boolean

function Y + A

• B or Y + A ) B in positive logic.

ORDERING INFORMATION

T

A

−40°C to 125°C

†

For the most current package and ordering information, see the Package Option Addendum at the end of
this document, or see the TI web site at http://www.ti.com.

‡

Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

SOIC − D Tape and reel SN74AHCT32QDRQ1 AHCT32Q

TSSOP − PW Tape and reel SN74AHCT32QPWRQ1 AHCT32Q

PACKAGE

‡

FUNCTION TABLE

(each gate)

INPUTS

A B

H X H

X HH

L L L

ORDERABLE

PART NUMBER

OUTPUT

Y

D OR PW PACKAGE

(TOP VIEW)

1

14

13

12

11

10

V

CC

4B
4A
4Y
3B

9

3A

8

3Y

1A

2

1B

3

1Y

4

2A

5

2B

6

2Y

GND

{

7

TOP-SIDE
MARKING

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

EPIC is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

†

1

1A

2

1B

4

2A

5

2B

9

3A

10

3B

12

4A

13

4B

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

≥ 1

3

1Y

6

2Y

8

3Y

11

4Y

Copyright  2008, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN74AHCT32-Q1
QUADRUPLE 2-INPUT POSITIVE-OR GATE

SCLS528A − AUGUST 2003 − REVISED APRIL 2008

logic diagram, each gate (positive logic)

A

B

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Y

‡

Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(V

< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(VO = 0 to V

O

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

V

V

V

V

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 20 ns/V

T

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 4.5 5.5 V

CC

High-level input voltage 2 V

IH

Low-level input voltage 0.8 V

IL

Input voltage 0 5.5 V

I

Output voltage 0 V

O

High-level output current −8 mA

Low-level output current 8 mA

Operating free-air temperature −40 125 °C

A

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC

V

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FROM

TO

LOAD

SN74AHCT32-Q1

QUADRUPLE 2-INPUT POSITIVE-OR GATE

SCLS528A − AUGUST 2003 − REVISED APRIL 2008

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

T

= 25°C

PARAMETER TEST CONDITIONS V

V

OH

V

OL

I

I

I

CC

†

∆I

CC

C

i

†

This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.

IOH = −50 mA

IOH = −8 mA

IOL = 50 mA

IOL = 8 mA

VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1 mA

VI = VCC or GND, IO = 0 5.5 V 2 20 mA

One input at 3.4 V,
Other inputs at V

VI = VCC or GND 5 V 2 10 pF

or GND

CC

CC

4.5 V

4.5 V

5.5 V 1.35 1.5 mA

switching characteristics over recommended operating free-air temperature range,

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

V

CC

PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

FROM TO LOAD

(INPUT)

A or B Y CL = 15 pF

A or B Y CL = 50 pF

(OUTPUT)

CAPACITANCE

A

MIN TYP MAX

4.4 4.5 4.4

3.94 3.8

0.36 0.44

T

= 25°C

A

MIN TYP MAX

5 6.9 1 8

5 6.9 1 8

5.5 7.9 1 9

5.5 7.9 1 9

MIN MAX UNIT

0.1 0.1

MIN MAX UNIT

V

V

ns

ns

noise characteristics, V

V

OL(P)

V

OL(V)

V

OH(V)

V

IH(D)

V

IL(D)

NOTE 4: Characteristics are for surface-mount packages only.

Quiet output, maximum dynamic V

Quiet output, minimum dynamic V

Quiet output, minimum dynamic V

High-level dynamic input voltage 2 V

Low-level dynamic input voltage 0.8 V

operating characteristics, V

C

Power dissipation capacitance No load, f = 1 MHz 11.5 pF

pd

= 5 V, CL = 50 pF, TA = 25°C (see Note 4)

CC

PARAMETER MIN TYP MAX UNIT

OL

OL

OH

= 5 V, TA = 25°C

CC

PARAMETER TEST CONDITIONS TYP UNIT

0.4 0.8 V

−0.4 −0.8 V

4.5 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN74AHCT32-Q1
QUADRUPLE 2-INPUT POSITIVE-OR GATE

SCLS528A − AUGUST 2003 − REVISED APRIL 2008

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

(see Note A)

Test
Point

C

L

From Output

Under Test

(see Note A)

C

L

RL = 1 kΩ

S1

V

CC

GND

Open

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open Drain

Open

V

CC

GND

V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

t

w

Input

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

Input

t

PLH

In-Phase

Output

Out-of-Phase

Output

t

PHL

50% V

50% V

CC

CC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z
D. The outputs are measured one at a time with one input transition per measurement.

3-STATE AND OPEN-DRAIN OUTPUTS

LOAD CIRCUIT FOR

Timing Input

3 V

Data Input

0 V

t

PHL

50% V

t

PLH

50% V

CC

CC

3 V

0 V

V

V

V

V

OH

OL

OH

OL

Output

Control

Output

Waveform 1

S1 at V

CC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

1.5 V

t

t

su

h

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V1.5 V 1.5 V

t

t

PZL

PZH

50% V

50% V

CC

CC

t

PLZ

VOL + 0.3 V

t

PHZ

VOH − 0.3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

= 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.

O

3 V

0 V

3 V

0 V

3 V

0 V

≈V

V

OL

V

OH

≈0 V

CC

Figure 1. Load Circuit and Voltage Waveforms

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com 15-Mar-2010

PACKAGING INFORMATION

Orderable Device Status

SN74AHCT32QDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74AHCT32QDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74AHCT32QPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74AHCT32QPWRQ1 ACTIVE TSSOP PW 14 2000 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

no Sb/Br)

no Sb/Br)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AHCT32-Q1 :

Catalog: SN74AHCT32

•

Enhanced Product: SN74AHCT32-EP

•

Military: SN54AHCT32

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Enhanced Product - Supports Defense, Aerospace and Medical Applications

•

Military - QML certified for Military and Defense Applications

•

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