Datasheet SN74AHCT273DBR, SN74AHCT273DGVR, SN74AHCT273DW, SN74AHCT273DWR, SN74AHCT273N Datasheet (Texas Instruments)
...
OUTPUT
SN54AHCT273, SN74AHCT273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Contain Eight Flip-Flops With Single-Rail
Outputs
D
Direct Clear Input
D
Individual Data Input to Each Flip-Flop
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
SN74AHCT273 . .. DB, DGV, DW, N, OR PW PACKAGE
SN54AHCT273 ...J OR W PACKAGE
(TOP VIEW)
CLR
GND
SN54AHCT273 . . . FK PACKAGE
2D
2Q
3Q
3D
4D
1
1Q
2
1D
3
2D
4
2Q
5
3Q
6
3D
7
4D
8
9
4Q
10
(TOP VIEW)
1D1QCLR
3 2 1 20 19
4
5
6
7
8
9 10 11 12 13
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
CC
V
8Q
8D
18
7D
17
16
7Q
15
6Q
14
6D
description
4Q
GND
CLK
5Q
5D
These devices are positive-edge-triggered D-type
flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the
D input has no effect at the output.
The SN54AHCT273 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT273 is characterized for operation from –40°C to 85 °C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK D
CLR
L X X L
H ↑ HH
H ↑ LL
H L X Q
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OUTPUT
Q
0
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
SN54AHCT273, SN74AHCT273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
CLR
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
11
3
4
7
8
13
14
17
18
R
C1
1D
logic diagram (positive logic)
CLK
1D
3 4 7 8 13 14 17 18
11
1D
C1
R
2D
1D
C1
R
3D
1D
R
C1
4D
5D
1D
C1
R
1D
R
C1
12
15
16
19
2
1Q
5
2Q
6
3Q
9
4Q
5Q
6Q
7Q
8Q
6D
1D
C1
R
7D
1D
R
C1
8D
1D
C1
R
1
CLR
2 5 6 9 12 15 16 19
1Q
2Q
3Q
logic diagram, each flip-flop (positive logic)
C
D
CLK(I)
R
TG
C
C
TG
C
C
C
4Q
TG
5Q
C
C
C
TG
C
6Q
7Q
8Q
Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54AHCT273, SN74AHCT273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, I
Output clamp current, I
(see Note 1) –0.5 V to V
O
(V
IK
I
OK
Continuous output current, I
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AHCT273 SN74AHCT273
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall time 20 20 ns/V
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current –8 –8 mA
Low-level output current 8 8 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
CC
0 V
CC
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54AHCT273, SN74AHCT273
PARAMETER
TEST CONDITIONS
V
UNIT
V
4.5 V
V
V
4.5 V
V
UNIT
twPulse duration
ns
t
Set
ns
PARAMETER
UNIT
f
MH
CLKQC
pF
ns
CLKQC
pF
ns
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
OH
OL
I
I
I
CC
∆I
CC
C
i
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
VI = VCC or GND, IO = 0 5.5 V 4 40 40
One input at 3.4 V ,
‡
Other inputs at VCC or GND
VI = VCC or GND 5 V 2.5 10 10 pF
5.5 V 1.35 1.5 1.5
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
CLR low 5 6 6
CLK high or low 5 6.5 6.5
su
t
h
up time
Hold time, data after CLK↑ 0 0 0 ns
Data before CLK↑
CLR
before CLK↑
TA = 25°C SN54AHCT273 SN74AHCT273
MIN TYP MAX MIN MAX MIN MAX
4.4 4.5 4.4 4.4
3.94 3.8 3.8
0.1 0.1 0.1
0.36 0.44 0.44
TA = 25°C SN54AHCT273 SN74AHCT273
MIN MAX MIN MAX MIN MAX
5 5 5
2.5 2.5 2.5
m
A
m
A
m
A
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PHL
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
t
sk(o)
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.
CLR Q
CLR Q
CL = 15 pF 75** 120** 65** 65
CL = 50 pF 50 75 45 45
CL = 15 pF 7.5** 10** 1** 11.6** 1 11.6 ns
p
= 15
L
CL = 50 pF 8.5 11 1 12.6 1 12.6 ns
p
= 50
L
CL = 50 pF 1*** 1 ns
TA = 25°C SN54AHCT273 SN74AHCT273
MIN TYP MAX MIN MAX MIN MAX
5.5** 7.5** 1** 8.8** 1 8.8
5.8** 8.2** 1** 10** 1 10
6.5 8.5 1 9.8 1 9.8
6.8 9.2 1 11 1 11
z
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
UNIT
SN54AHCT273, SN74AHCT273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only .
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2 V
Low-level dynamic input voltage 0.8 V
= 5 V, CL = 50 pF, TA = 25°C (see Note 4)
CC
OL
OL
OH
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance No load, f = 1 MHz 27 pF
pd
SN74AHCT273
MIN TYP MAX
0.76 V
–0.48 V
4.4 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54AHCT273, SN74AHCT273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
C
V
RL = 1 kΩ
L
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
50% V
t
PHL
50% V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3-STATE AND OPEN-DRAIN OUTPUTS
CC
CC
t
PHL
50% V
t
PLH
50% V
LOAD CIRCUIT FOR
Timing Input
3 V
0 V
3 V
0 V
V
OH
CC
V
V
CC
V
OL
OH
OL
(see Note B)
(see Note B)
Data Input
Output
Control
Output
Waveform 1
S1 at V
CC
Output
Waveform 2
S1 at GND
1.5 V
t
CC
CC
h
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V1.5 V 1.5 V
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
3 V
0 V
3 V
0 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
6
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 2000, Texas Instruments Incorporated
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