Texas Instruments SN74AHCT244DBLE, SN74AHCT244DBR, SN74AHCT244DGVR, SN74AHCT244DW, SN74AHCT244DWR Datasheet
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SN54AHCT244, SN74AHCT244
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS228J – OCTOBER 1995 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
description
These octal buffers/drivers are designed
specifically to improve both the performance and
density of 3-state memory-address drivers, clock
drivers, and bus-oriented receivers and
transmitters.
The ’AHCT244 devices are organized as two 4-bit
buffers/line drivers with separate output-enable
(OE
) inputs. When OE is low, the device passes
data from the A inputs to the Y outputs. When OE
is high, the outputs are in the high-impedance
state.
SN74AHCT244 . . . DB, DGV, DW, N, OR PW PACKAGE
SN54AHCT244 ...J OR W PACKAGE
(TOP VIEW)
1OE
1
1A1
2
2Y4
3
1A2
4
2Y3
5
1A3
6
2Y2
7
1A4
8
9
2Y1
GND
SN54AHCT244 . . . FK PACKAGE
1A2
2Y3
1A3
2Y2
1A4
10
(TOP VIEW)
2Y4
1A1
3212019
4
5
6
7
8
910111213
20
19
18
17
16
15
14
13
12
11
1OE
V
CC
V
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
18
17
16
15
14
CC
1Y1
2A4
1Y2
2A3
1Y3
T o ensure the high-impedance state during power
up or power down, OE should be tied to V
CC
2Y1
GND
2A1
1Y4
2A2 2OE
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
The SN54AHCT244 is characterized for
operation over the full military temperature range
of –55°C to 125°C. The SN74AHCT244 is
characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS
OE A
L H H
L LL
H X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OUTPUT
Y
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54AHCT244, SN74AHCT244
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS228J – OCTOBER 1995 – REVISED JANUARY 2000
logic symbol
1OE
1A1
1A2
1A3
1A4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1
2
4
6
8
EN
18
16
14
12
1Y1
1Y2
1Y3
1Y4
2OE
2A1
2A2
2A3
2A4
logic diagram (positive logic)
1
1OE
218
1A1
416
1A2
1Y1
1Y2
2OE
2A1
2A2
19
11
13
15
17
19
11 9
13 7
EN
2Y1
2Y2
9
2Y1
7
2Y2
5
2Y3
3
2Y4
614
1A3
812
1A4
1Y3
1Y4
15 5
2A3
17 3
2A4
2Y3
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(V
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
V
4.5 V
V
V
4.5 V
V
SN54AHCT244, SN74AHCT244
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS228J – OCTOBER 1995 – REVISED JANUARY 2000
recommended operating conditions (see Note 3)
SN54AHCT244 SN74AHCT244
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current –8 –8 mA
Low-level output current 8 8 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
VI = VCC or GND, IO = 0 5.5 V 4 40 40
One input at 3.4 V ,
†
Other inputs at VCC or GND
VI = VCC or GND 5 V 2.5 10 10 pF
VO = VCC or GND 5 V 3 pF
I
I
I
∆I
C
C
OH
OL
OZ
I
CC
CC
i
o
, literature number SCBA004.
CC
5.5 V 1.35 1.5 1.5 mA
TA = 25°C SN54AHCT244 SN74AHCT244
MIN TYP MAX MIN MAX MIN MAX
4.4 4.5 4.4 4.4
3.94 3.8 3.8
0.1 0.1 0.1
0.36 0.44 0.44
CC
0 V
CC
V
m
A
m
A
m
A
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54AHCT244, SN74AHCT244
PARAMETER
UNIT
AYC
15 pF
ns
OE
Y
C
15 pF
ns
OE
Y
C
pF
ns
AYC
pF
ns
OE
Y
C
pF
ns
OE
Y
C
pF
ns
PARAMETER
UNIT
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS228J – OCTOBER 1995 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
CL = 50 pF 1** 1 ns
=
L
=
L
= 15
L
= 50
L
= 50
L
= 50
L
p
p
p
p
p
p
TA = 25°C SN54AHCT244 SN74AHCT244
MIN TYP MAX MIN MAX MIN MAX
5.4* 7.4* 1* 8.5* 1 8.5
5.4* 7.4* 1* 8.5* 1 8.5
7.7* 10.4* 1* 12* 1 12
7.7* 10.4* 1* 12* 1 12
5* 9.4* 1* 10* 1 10
5* 9.4* 1* 10* 1 10
5.9 8.4 1 9.5 1 9.5
5.9 8.4 1 9.5 1 9.5
8.2 11.4 1 13 1 13
8.2 11.4 1 13 1 13
8.8 11.4 1 13 1 13
8.8 11.4 1 13 1 13
noise characteristics, V
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only.
Quiet output, minimum dynamic V
High-level dynamic input voltage 2 V
Low-level dynamic input voltage 0.8 V
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 8.2 pF
pd
= 5 V, C
CC
CC
PARAMETER TEST CONDITIONS TYP UNIT
= 50 pF, TA = 25°C (see Note 4)
L
OH
= 5 V, T
= 25°C
A
SN74AHCT244
MIN TYP MAX
4.1 V
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54AHCT244, SN74AHCT244
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS228J – OCTOBER 1995 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
50% V
t
PHL
50% V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3-STATE AND OPEN-DRAIN OUTPUTS
CC
CC
LOAD CIRCUIT FOR
3 V
0 V
3 V
0 V
t
PHL
V
t
PLH
CC
CC
OH
V
OL
V
OH
V
OL
50% V
50% V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
1.5 V
t
CC
CC
h
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V1.5 V 1.5 V
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
3 V
0 V
3 V
0 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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