SN74AHCT1G14
SINGLE SCHMITT-TRIGGER INVERTER GATE
SCLS322K – MARCH 1996 – REVISED JANUARY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline Transistor (DBV, DCK)
Packages
description
The SN74AHCT1G14 contains a single inverter gate. The device performs the Boolean function Y = A.
The device functions as an independent inverter gate, but because of the Schmitt action, gates may have
different input threshold levels for positive- (VT+) and negative-going (VT–) signals.
The SN74AHCT1G14 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H L
L H
logic symbol
†
2
A
Y
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
A
Y
24
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critic al applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
NC
A
GND
V
CC
Y
NC – No internal connection
SN74AHCT1G14
SINGLE SCHMITT-TRIGGER INVERTER GATE
SCLS322K – MARCH 1996 – REVISED JANUARY 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DBV package 347°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 389°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN MAX UNIT
V
CC
Supply voltage 4.5 5.5 V
V
I
Input voltage 0 5.5 V
V
O
Output voltage 0 V
CC
V
I
OH
High-level output current –8 mA
I
OL
Low-level output current 8 mA
T
A
Operating free-air temperature –40 85 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX
MIN
MAX
UNIT
V
T+
4.5 V 0.9 2 0.9 2
Positi
ve-going
input threshold voltage
5.5 V 1.1 2 1.1 2
V
V
T–
4.5 V 0.5 1.6 0.5 1.6
N
egative-going
input threshold voltage
5.5 V 0.6 1.5 0.6 1.5
V
∆V
4.5 V 0.4 1.4 0.4 1.4
T
Hysteresis (VT+ – VT–)
5.5 V 0.5 1.6 0.4 1.6
V
IOH = –50 mA
4.4 4.5 4.4
V
OH
IOH = –8 mA
4.5 V
3.94 3.8
V
IOL = 50 mA
0.1 0.1
V
OL
IOL = 8 mA
4.5 V
0.36 0.44
V
I
I
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1
m
A
I
CC
VI = VCC or GND, IO = 0 5.5 V 1 10
m
A
C
i
VI = VCC or GND 5 V 2 10 10 pF
SN74AHCT1G14
SINGLE SCHMITT-TRIGGER INVERTER GATE
SCLS322K – MARCH 1996 – REVISED JANUARY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM TO LOAD
TA = 25°C
PARAMETER
(INPUT) (OUTPUT) CAPACITANCE
MIN TYP MAX
MIN
MAX
UNIT
t
PLH
p
4 7 1 8
t
PHL
A
Y
C
L
=
15 pF
4 7 1 8
ns
t
PLH
p
5.5 8 1 9
t
PHL
A
Y
C
L
=
50 pF
5.5 8 1 9
ns
operating characteristics, V
CC
= 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance No load, f = 1 MHz 12 pF
SN74AHCT1G14
SINGLE SCHMITT-TRIGGER INVERTER GATE
SCLS322K – MARCH 1996 – REVISED JANUARY 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% V
CC
3 V
3 V
0 V
0 V
t
h
t
su
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
Data Input
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
3 V
0 V
50% V
CC
50% V
CC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% V
CC
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
≈V
CC
0 V
50% V
CC
VOL + 0.3 V
50% V
CC
≈0 V
3 V
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
TEST S1
3 V
0 V
t
w
VOLTAGE WA VEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
V
CC
RL = 1 kΩ
GND
From Output
Under Test
C
L
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH – 0.3 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V1.5 V 1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 2000, Texas Instruments Incorporated
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