Datasheet SN74AHCT16541DGGR, SN74AHCT16541DGVR, SN74AHCT16541DL, SN74AHCT16541DLR Datasheet (Texas Instruments)
SN54AHCT16541, SN74AHCT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS339H – MARCH 1996 – REVISED JANUARY 2000
D
Members of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’AHCT16541 devices are noninverting 16-bit
buffers composed of two 8-bit sections with
separate output-enable signals. For either 8-bit
buffer section, the two output-enable (1OE1 and
1OE2
or 2OE1 and 2OE2) inputs must both be low
for the corresponding Y outputs to be active. If
either output-enable input is high, the outputs of
that 8-bit buffer section are in the high-impedance
state.
SN54AHCT16541 . . . WD PACKAGE
SN74AHCT16541 . . . DGG, DGV, OR DL PACKAGE
1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
V
CC
2Y5
2Y6
GND
2Y7
2Y8
2OE1
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE2
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHCT16541 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT16541 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit buffer/driver)
INPUTS
OE2 A
OE1
L L L L
L LH H
H XX Z
X H X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
OUTPUT
Y
Copyright 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54AHCT16541, SN74AHCT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS339H – MARCH 1996 – REVISED JANUARY 2000
logic symbol
†
1OE1
1OE2
2OE1
2OE2
1
48
24
25
47
1A1 1Y1
46
1A2
44
1A3 1Y3
43
1A4 1Y4
41
1A5 1Y5
40
1A6 1Y6
38
1A7 1Y7
37
1A8 1Y8
36
2A1 2Y1
35
2A2
33
2A3 2Y3
32
2A4 2Y4
30
2A5 2Y5
29
2A6 2Y6
27
2A7
26
2A8 2Y8
&
&
EN1
EN2
111
2
3
1Y2
5
6
8
9
11
12
2
13
14
16
17
19
20
22
23
2Y2
2Y7
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
1OE1
48
1OE2
47
1A1 1Y1
To Seven Other Channels To Seven Other Channels
2
2OE1
2OE2
2A1
24
25
36
13
2Y1
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54AHCT16541, SN74AHCT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS339H – MARCH 1996 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, I
Output clamp current, I
(see Note 1) –0.5 V to V
O
(V
IK
I
OK
Continuous output current, I
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AHCT16541 SN74AHCT16541
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 20 20 ns/V
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current –8 –8 mA
Low-level output current 8 8 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
CC
0 V
CC
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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SN54AHCT16541, SN74AHCT16541
PARAMETER
TEST CONDITIONS
V
UNIT
V
4.5 V
V
V
4.5 V
V
PARAMETER
UNIT
AYC
pF
ns
OE
Y
C
pF
ns
OE
Y
C
15 pF
ns
AYC
pF
ns
OE
Y
C
pF
ns
OE
Y
C
pF
ns
PARAMETER
UNIT
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS339H – MARCH 1996 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
OH
OL
I
I
I
OZ
I
CC
∆I
CC
C
i
C
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5
VI = VCC or GND, IO = 0 5.5 V 4 40 40
One input at 3.4 V ,
†
Other inputs at VCC or GND
VI = VCC or GND 5 V 2 10 10 pF
VO = VCC or GND 5 V 3 pF
5.5 V 1.35 1.5 1.5 mA
TA = 25°C SN54AHCT16541 SN74AHCT16541
MIN TYP MAX MIN MAX MIN MAX
4.4 4.5 4.4 4.4
3.94 3.8 3.8
0.1 0.1 0.1
0.36 0.44 0.44
m
A
m
A
m
A
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2 V
Low-level dynamic input voltage 0.8 V
= 5 V, C
CC
CL = 50 pF 1*** 1 ns
OL
OL
OH
p
= 15
L
p
= 15
L
p
=
L
p
= 50
L
p
= 50
L
p
= 50
L
= 50 pF, TA = 25°C (see Note 4)
L
TA = 25°C SN54AHCT16541 SN74AHCT16541
MIN TYP MAX MIN MAX MIN MAX
5.4** 8.5** 1** 10** 1 9.5
5.4** 8.5** 1** 10** 1 9.5
7.7** 10.4** 1** 12** 1 12
7.7** 10.4** 1** 12** 1 12
4.5** 10.4** 1** 12** 1 12
4.5** 10.4** 1** 12** 1 12
6.2 9.5 1 11 1 10.5
6 9.5 1 11 1 10.5
7.5 11.4 1 13 1 13
7.5 11.4 1 13 1 13
7 11.4 1 13 1 13
7 11.4 1 13 1 13
SN74AHCT16541
MIN TYP MAX
0.6 V
–0.3 V
4.6 V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
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SN54AHCT16541, SN74AHCT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS339H – MARCH 1996 – REVISED JANUARY 2000
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 12 pF
pd
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Test
Point
C
L
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
= 5 V, TA = 25°C
CC
PARAMETER TEST CONDITIONS TYP UNIT
V
CC
Open
GND
Open Drain
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V
t
h
Open
V
CC
GND
V
CC
From Output
Under Test
C
(see Note A)
3-STATE AND OPEN-DRAIN OUTPUTS
L
LOAD CIRCUIT FOR
RL = 1 kΩ
3 V
0 V
S1
Timing Input
Data Input
3 V
0 V
3 V
0 V
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
50% V
50% V
CC
CC
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
50% V
t
PLH
50% V
3 V
0 V
V
CC
V
V
CC
V
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
1.5 V 1.5 V1.5 V 1.5 V
t
PZL
50% V
CC
t
PZH
50% V
CC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
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