Datasheet SN74AHCT16245DGVR, SN74AHCT16245DL, SN74AHCT16245DLR Datasheet (Texas Instruments)
OPERATION
SN54AHCT16245, SN74AHCT16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS335I – MARCH 1996 – REVISED JANUARY 2000
D
Members of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’AHCT16245 devices are 16-bit (dual-octal)
noninverting 3-state transceivers designed for
synchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the direction-control (DIR) input. The
output-enable (OE
the device so that the buses are effectively
isolated.
) input can be used to disable
SN54AHCT16245 . . . WD PACKAGE
SN74AHCT16245 . . . DGG, DGV, OR DL PACKAGE
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHCT16245 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT16245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit transceiver)
INPUTS
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
SN54AHCT16245, SN74AHCT16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS335I – MARCH 1996 – REVISED JANUARY 2000
logic symbol
†
1OE
1DIR
2OE
2DIR
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
48
1
25
24
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
G3
3 EN1 [BA]
3 EN2 [AB]
G6
6 EN4 [BA]
6 EN5 [AB]
1
4
2
1B1
2
5
11
12
13
14
16
17
19
20
22
23
3
1B2
5
1B3
6
1B4
8
1B5
9
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
1DIR
1A1
47
To Seven Other Channels
48
1OE
2
1B1
2DIR
2A1
24
36
To Seven Other Channels
25
13
2OE
2B1
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54AHCT16245, SN74AHCT16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS335I – MARCH 1996 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, I
Output clamp current, I
(see Note 1) –0.5 V to V
O
(V
IK
I
OK
Continuous output current, I
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AHCT16245 SN74AHCT16245
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 20 20 ns/V
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 5.5 0 5.5 V
I
Input/output voltage, A or B pins 0 V
IO
High-level output current –8 –8 mA
Low-level output current 8 8 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
CC
0 V
CC
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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3
SN54AHCT16245, SN74AHCT16245
PARAMETER
TEST CONDITIONS
V
UNIT
V
4.5 V
V
V
4.5 V
V
PARAMETER
UNIT
A or B
B or A
C
pF
ns
OE
A or B
C
pF
ns
OE
A or B
C
15 pF
ns
A or B
B or A
C
pF
ns
OE
A or B
C
pF
ns
OE
A or B
C
pF
ns
PARAMETER
UNIT
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS335I – MARCH 1996 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
OH
OL
I
OE or DIR VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1mA
I
†
I
A or B inputs VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5mA
OZ
I
CC
‡
∆I
CC
C
OE or DIR VI = VCC or GND 5 V 2.5 10 10 pF
i
C
A or B inputs VI = VCC or GND 5 V 4 pF
io
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†
For I/O ports, the parameter IOZ includes the input leakage current.
‡
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
VI = VCC or GND, IO = 0 5.5 V 4 40 40mA
One input at 3.4 V ,
Other inputs at VCC or GND
5.5 V 1.35 1.5 1.5 mA
TA = 25°C SN54AHCT16245 SN74AHCT16245
MIN TYP MAX MIN MAX MIN MAX
4.4 4.5 4.4 4.4
3.94 3.8 3.8
0.1 0.1 0.1
0.36 0.44 0.44
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2 V
Low-level dynamic input voltage 0.8 V
= 5 V, C
CC
CL = 50 pF 1*** 1 ns
OL
OL
OH
p
= 15
L
p
= 15
L
p
=
L
p
= 50
L
p
= 50
L
p
= 50
L
= 50 pF, TA = 25°C (see Note 4)
L
TA = 25°C SN54AHCT16245 SN74AHCT16245
MIN TYP MAX MIN MAX MIN MAX
4.5** 8.5** 1** 10** 1 9.5
4.5** 8.5** 1** 10** 1 9.5
8.9** 13** 1** 14** 1 14
8.9** 13** 1** 14** 1 14
9.2** 14** 1** 15** 1 15
9.2** 14** 1** 15** 1 15
7 9.5 1 11 1 10.5
5.3 9.5 1 11 1 10.5
8.3 14 1 15 1 15
8.3 14 1 15 1 15
8 14 1 15 1 15
8 14 1 15 1 15
SN74AHCT16245
MIN TYP MAX
0.6 V
–0.6 V
4.8 V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT16245, SN74AHCT16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS335I – MARCH 1996 – REVISED JANUARY 2000
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 17 pF
pd
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Test
Point
C
L
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
= 5 V, TA = 25°C
CC
PARAMETER TEST CONDITIONS TYP UNIT
V
CC
Open
GND
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
1.5 V
t
h
Open
V
CC
GND
V
CC
From Output
Under Test
C
(see Note A)
L
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
RL = 1 kΩ
3 V
0 V
S1
Timing Input
Data Input
3 V
0 V
3 V
0 V
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
50% V
50% V
CC
CC
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
50% V
t
PLH
50% V
CC
CC
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
1.5 V 1.5 V1.5 V 1.5 V
t
PZL
50% V
CC
t
PZH
50% V
CC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
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