
SN54AHCT157, SN74AHCT157
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SCLS347I – MAY 1996 – REVISED JANUAR Y 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
description
These quadruple 2-line to 1-line data
selectors/multiplexers are designed for 4.5-V to
5.5-V V
The ’AHCT157 devices feature a common strobe
(G) input. When the strobe is high, all outputs are
low. When the strobe is low, a 4-bit word is
selected from one of two sources and is routed to
the four outputs. The devices provide true data.
The SN54AHCT157 is characterized for
operation over the full military temperature range
of –55°C to 125°C. The SN74AHCT157 is
characterized for operation from –40°C to 85°C.
operation.
CC
SN54AHCT157 ...J OR W PACKAGE
SN74AHCT157 . . . D, DB, DGV, N, OR PW PACKAGE
SN54AHCT157 . . . FK PACKAGE
1B
1Y
NC
2A
2B
NC – No internal connection
(TOP VIEW)
1
A/B
2
1A
3
1B
4
1Y
5
2A
6
2B
7
2Y
GND
8
(TOP VIEW)
1A
3212019
4
5
6
7
8
910111213
2Y
A/B
GND
16
15
14
13
12
11
10
NC
NC
9
CC
V
3Y
V
G
4A
4B
4Y
3A
3B
3Y
G
18
17
16
15
14
3B
CC
4A
4B
NC
4Y
3A
G A/B A B
H X X X L
L LLX L
L LHX H
L HXL L
L H X H H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
FUNCTION TABLE
INPUTS
OUTPUT
Y
Copyright 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1

SN54AHCT157, SN74AHCT157
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SCLS347I – MAY 1996 – REVISED JANUAR Y 2000
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
†
15
A/B
1A
1B
2A
2B
3A
3B
4A
4B
G
1
2
3
5
6
11
10
14
13
EN
G1
1
1
MUX
logic diagram (positive logic)
2
1A
3
1B
12
4
1Y
7
2Y
9
3Y
4Y
4
1Y
5
2A
6
2B
11
3A
10
3B
14
4A
13
4B
15
G
1
A/B
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
12
7
2Y
9
3Y
4Y
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265