Datasheet SN74AHCT132D, SN74AHCT132DBR, SN74AHCT132DGVR, SN74AHCT132DR, SN74AHCT132N Datasheet (Texas Instruments)

SN54AHCT132, SN74AHCT132

QUADRUPLE POSITIVE-NAND GATES

WITH SCHMITT-TRIGGER INPUTS

SCLS366F – MAY 1997 – REVISED JANUAR Y 2000

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Inputs Are TTL-Voltage Compatible

D

Operation From Very Slow Input
Transitions

D

T emperature-Compensated Threshold
Levels

D

High Noise Immunity

D

Same Pinouts as ’AHCT00

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

D

Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs

description

The ’AHCT132 devices are quadruple
positive-NAND gates.

SN54AHCT132 ...J OR W PACKAGE

SN74AHCT132 . . . D, DB, DGV, N, OR PW PACKAGE

SN54AHCT132 . . . FK PACKAGE

1Y

NC

2A

NC

2B

NC – No internal connection

(TOP VIEW)

1A

1

1B

2

1Y

3

2A

4

2B

5
6

2Y

GND

7

(TOP VIEW)

1B1ANC

3212019

4
5
6
7
8

910111213

2Y

GND

NC

14
13
12
11
10

9
8

CC

V

3Y

V
4B
4A
4Y
3B
3A
3Y

4B

18
17
16
15
14

3A

CC

4A
NC
4Y
NC
3B

These devices perform the Boolean function Y = A • B or Y = A + B in positive logic.
Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels

for positive- and negative-going signals.
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give

clean jitter-free output signals.
The SN54AHCT132 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74AHCT132 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each gate)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

INPUTS

A B

H H L

L XH

X L H

OUTPUT

Y

Copyright  2000, Texas Instruments Incorporated

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1

SN54AHCT132, SN74AHCT132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS

SCLS366F – MAY 1997 – REVISED JANUAR Y 2000

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.

†

1

1A
1B
2A
2B
3A
3B
4A
4B

2
4
5
9
10
12
13

&

logic diagram, each gate (positive logic)

A

B

3

1Y

6

2Y

8

3Y

11

4Y

Y

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) –0.5 V to V
Input clamp current, I
Output clamp current, I
Continuous output current, I

(V

< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(V

= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

O

Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

2

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UNIT

PARAMETER

TEST CONDITIONS

V

UNIT

Positi

t

V

N

t

V

Hyst

V

V

4.5 V

V

V

4.5 V

V

SN54AHCT132, SN74AHCT132

QUADRUPLE POSITIVE-NAND GATES

WITH SCHMITT-TRIGGER INPUTS

SCLS366F – MAY 1997 – REVISED JANUAR Y 2000

recommended operating conditions (see Note 3)

SN54AHCT132 SN74AHCT132

MIN MAX MIN MAX

V
V
V
I

OH

I

OL

T

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†

This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.

Supply voltage 4.5 5.5 4.5 5.5 V

CC

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

High-level output current –8 –8 mA
Low-level output current 8 8 mA
Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

V

T+

T–

T

eresis

OH

OL

I
CC

CC

i

p

p

IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
VI = VCC or GND, IO = 0 5.5 V 2 20 20

†

One input at 3.4 V ,
Other inputs at VCC or GND

VI = VCC or GND 5 V 2 10 10 pF

ve-going inpu

threshold voltage

V
egative-going inpu
threshold voltage

∆V

(VT+ – VT–)

I

I

∆I

C

, literature number SCBA004.

CC

4.5 V 0.9 1.9 0.9 1.9 0.9 1.9

5.5 V 1 2.1 1 2.1 1 2.1

4.5 V 0.5 1.5 0.5 1.5 0.5 1.5

5.5 V 0.6 1.7 0.6 1.7 0.6 1.7

4.5 V 0.3 1.4 0.3 1.4 0.3 1.4

5.5 V 0.3 1.5 0.3 1.5 0.3 1.5

5.5 V 1.35 1.5 1.5 mA

TA = 25°C SN54AHCT132 SN74AHCT132

MIN TYP MAX MIN MAX MIN MAX

4.4 4.5 4.4 4.4

3.94 3.8 3.8

0.1 0.1 0.1

0.36 0.5 0.44

CC

0 V

CC

V

m

A

m

A

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

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SN54AHCT132, SN74AHCT132

PARAMETER

UNIT

A or B

Y

C

15 pF

ns

A or B

Y

C

50 pF

ns

PARAMETER

UNIT

QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS

SCLS366F – MAY 1997 – REVISED JANUAR Y 2000

switching characteristics over recommended operating free-air temperature range,
V

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

t

PLH

t

PHL

t

PLH

t

PHL

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

p

=

L

p

=

L

TA = 25°C SN54AHCT132 SN74AHCT132

MIN TYP MAX MIN MAX MIN MAX

5.5* 8* 1* 9* 1 9

4.5* 6* 1* 7* 1 7

6.5 9 1 10 1 10

5.5 7 1 8 1 8

noise characteristics, V

V

OL(P)

V

OL(V)

V

OH(V)

V

IH(D)

V

IL(D)

NOTE 4: Characteristics are for surface-mount packages only.

Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2 V
Low-level dynamic input voltage 0.8 V

operating characteristics, V

C

Power dissipation capacitance No load, f = 1 MHz 15 pF

pd

= 5 V, C

CC

CC

PARAMETER TEST CONDITIONS TYP UNIT

= 50 pF, TA = 25°C (see Note 4)

L

OL
OL
OH

= 5 V, TA = 25°C

SN74AHCT132

MIN TYP MAX

0.5 0.8 V

–0.28 –0.8 V

5 V

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

4

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From Output

Under Test

(see Note A)

SN54AHCT132, SN74AHCT132

QUADRUPLE POSITIVE-NAND GATES

WITH SCHMITT-TRIGGER INPUTS

SCLS366F – MAY 1997 – REVISED JANUAR Y 2000

PARAMETER MEASUREMENT INFORMATION

V

Test
Point

C

L

From Output

Under Test

(see Note A)

C

L

RL = 1 kΩ

S1

CC

Open

GND

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open Drain

Open

V

CC

GND
V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

t

w

Input

Input

In-Phase

Output

Out-of-Phase

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

50% V

t

PHL

50% V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

3-STATE AND OPEN-DRAIN OUTPUTS

CC

CC

LOAD CIRCUIT FOR

3 V

0 V

3 V

0 V

t

PHL

V

t

PLH

CC

CC

OH

V

OL

V

OH

V

OL

50% V

50% V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at V

(see Note B)

Waveform 2

(see Note B)

CC

Output

S1 at GND

1.5 V

t

CC

CC

h

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V1.5 V 1.5 V

t

PZL

50% V

t

PZH

50% V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

3 V

0 V

3 V

0 V

3 V

0 V

≈V

V

OL

V

OH

≈0 V

CC

Figure 1. Load Circuit and Voltage Waveforms

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