Datasheet SN74AHCT02DGVR, SN74AHCT02DR, SN74AHCT02N, SN74AHCT02PWLE, SN74AHCT02PWR Datasheet (Texas Instruments)

SN54AHCT02, SN74AHCT02

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Inputs Are TTL-Voltage Compatible

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs

description

These devices contain four independent 2-input
NOR gates that perform the Boolean function
Y = A

S

B or Y = A + B in positive logic.

The SN54AHCT02 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AHCT02 is characterized for
operation from –40°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A B

Y

H X L
X HL
L L H

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

1
2
3
4
5
6
7

14
13
12
11
10

9
8

1Y
1A
1B
2Y
2A
2B

GND

V

CC

4Y
4B
4A
3Y
3B
3A

SN54AHCT02 ...J OR W PACKAGE

SN74AHCT02 . . . D, DB, DGV, N, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

4
5
6
7
8

18
17
16
15
14

4B
NC
4A
NC
3Y

1B

NC

2Y

NC

2A

1A1YNC

3A

3B

V

4Y

2B

GND

NC

SN54AHCT02 . . . FK PACKAGE

(TOP VIEW)

CC

NC – No internal connection

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV , J, N, PW, and W packages.

2

1A

3

1B

1Y

1

5

2A

6

2B

2Y

4

8

3A

9

3B

3Y

10

11

4A

12

4B

4Y

13

≥ 1

logic diagram (positive logic)

2

1A

3

1B

1Y

1

8

3A

9

3B

3Y

10

5

2A

6

2B

2Y

4

11

4A

12

4B

4Y

13

Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

CC

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

SN54AHCT02, SN74AHCT02

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

SN54AHCT02 SN74AHCT02

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 4.5 5.5 4.5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 0 5.5 0 5.5 V

V

O

Output voltage 0 V

CC

0 V

CC

V

I

OH

High-level output current –8 –8 mA

I

OL

Low-level output current 8 8 mA
∆t/∆v Input transition rise or fall rate 20 20 ns/V
T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54AHCT02 SN74AHCT02

PARAMETER

TEST CONDITIONS

V

CC

MIN TYP MAX MIN MAX MIN MAX

UNIT

IOH = –50 mA

4.4 4.5 4.4 4.4

V

OH

IOH = –8 mA

4.5 V

3.94 3.8 3.8

V

IOL = 50 mA

0.1 0.1 0.1

V

OL

IOL = 8 mA

4.5 V

0.36 0.44 0.44

V

I

I

VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1

m

A

I

CC

VI = VCC or GND, IO = 0 5.5 V 2 20 20

m

A

∆I

CC

†

One input at 3.4 V ,
Other inputs at GND or V

CC

5.5 V 1.35 1.5 1.5 mA

C

i

VI = VCC or GND 5 V 4 10 10 pF

* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†

This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.

switching characteristics over recommended operating free-air temperature range,
V

CC

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

FROM TO LOAD

TA = 25°C SN54AHCT02 SN74AHCT02

PARAMETER

(INPUT) (OUTPUT) CAPACITANCE

MIN TYP MAX MIN MAX MIN MAX

UNIT

t

PLH

p

2.4** 5.5** 1** 6.5** 1 6.5

t

PHL

A or B

Y

C

L

=

15 pF

3.5** 5.5** 1** 6.5** 1 6.5

ns

t

PLH

p

3.4 7.5 1 8.5 1 8.5

t

PHL

A or B

Y

C

L

=

50 pF

4.5 7.5 1 8.5 1 8.5

ns

** On products compliant to MIL-PRF-38535, this parameter is not production tested.

SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

noise characteristics, V

CC

= 5 V, CL = 50 pF, TA = 25°C (see Note 4)

SN74AHCT02

PARAMETER

MIN TYP MAX

UNIT

V

OL(P)

Quiet output, maximum dynamic V

OL

0.8 V

V

OL(V)

Quiet output, minimum dynamic V

OL

–0.8 V

V

OH(V)

Quiet output, minimum dynamic V

OH

4.7 V

V

IH(D)

High-level dynamic input voltage 2 V

V

IL(D)

Low-level dynamic input voltage 0.8 V

NOTE 4: Characteristics are for surface-mount packages only.

operating characteristics, V

CC

= 5 V, T

A

= 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

pd

Power dissipation capacitance No load, f = 1 MHz 17 pF

SN54AHCT02, SN74AHCT02

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

50% V

CC

3 V

3 V

0 V

0 V

t

h

t

su

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data Input

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

3 V

0 V

50% V

CC

50% V

CC

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

50% V

CC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

Output

Control

Output

Waveform 1

S1 at V

CC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

≈V

CC

0 V

50% V

CC

VOL + 0.3 V

50% V

CC

≈0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open Drain

Open

V

CC

GND

V

CC

TEST S1

3 V

0 V

t

w

VOLTAGE WAVEFORMS

PULSE DURATION

Input

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

S1

V

CC

RL = 1 kΩ

GND

From Output

Under Test

C

L

(see Note A)

Test
Point

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Open

VOH – 0.3 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V1.5 V 1.5 V

Figure 1. Load Circuit and Voltage Waveforms

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  2000, Texas Instruments Incorporated