ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
description
The ’AHC74 dual positive-edge-triggered devices
are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR)
inputs sets or resets the outputs, regardless of the
levels of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting
the setup time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at the D input can be changed without affecting the
levels at the outputs.
SN54AHC74 ...J OR W PACKAGE
SN74AHC74 . . . D, DB, DGV, N, OR PW PACKAGE
1CLR
1CLK
1PRE
SN54AHC74 . . . FK PACKAGE
1CLK
NC
1PRE
NC
1Q
NC – No internal connection
(TOP VIEW)
1
1D
2
3
4
1Q
5
6
1Q
GND
7
(TOP VIEW)
1D
3212019
4
5
6
7
8
910111213
1Q
1CLR
NC
NC
GND
14
13
12
11
10
9
8
CC
V
2Q
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
2CLR
18
17
16
15
14
2Q
2D
NC
2CLK
NC
2PRE
The SN54AHC74 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AHC74 is characterized for
operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54AHC74, SN74AHC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000
FUNCTION TABLE
(each flip-flop)
INPUTS
PRECLRCLKDQQ
LHXXHL
HLXXLH
LLXXH†H
HH↑HHL
HH↑LLH
HHLXQ
†
This configuration is nonstable; that is, it does not
persist when PRE
(high) level.
or CLR returns to its inactive
OUTPUTS
0
†
Q
0
logic symbol
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
‡
1PRE
1CLK
1D
1CLR
2PRE
2CLK
2D
2CLR
4
3
2
1
10
11
12
13
S
C1
1D
R
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
C
TG
5
1Q
6
1Q
9
2Q
8
2Q
Q
2
CLR
C
D
TG
C
C
C
TG
C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C
TG
Q
C
UNIT
mA
mA
∆t/∆vInput transition rise or fall rate
ns/V
SN54AHC74, SN74AHC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
VI = VCC or GND0 V to 5.5 V±0.1±1*±1
VI = VCC or GND,IO = 05.5 V22020
VI = VCC or GND5 V21010pF
3 V2.932.92.9
4.5 V4.44.54.44.4
2 V0.10.10.1
3 V0.10.10.1
4.5 V0.10.10.1
TA = 25°CSN54AHC74SN74AHC74
MINTYPMAXMINMAXMINMAX
V
V
m
A
m
A
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°CSN54AHC74SN74AHC74
MINMAXMINMAXMINMAX
PRE or CLR low677
CLK677
su
t
h
up time before
Hold time, data after CLK↑0.50.50.5ns
Data677
PRE or CLR inactive555
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°CSN54AHC74SN74AHC74
MINMAXMINMAXMINMAX
PRE or CLR low555
CLK555
su
t
h
up time before
Hold time, data after CLK↑0.50.50.5ns
Data555
PRE or CLR inactive333
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
UNIT
f
MH
PRE
CLR
Q
Q
C
15 pF
ns
CLK
Q
Q
C
pF
ns
PRE
CLR
Q
Q
C
50 pF
ns
CLK
Q
Q
C
50 pF
ns
PARAMETER
UNIT
f
MH
PRE
CLR
Q
Q
C
pF
ns
CLK
Q
Q
C
pF
ns
PRE
CLR
Q
Q
C
50 pF
ns
CLK
Q or Q
C
pF
ns
PARAMETER
UNIT
SN54AHC74, SN74AHC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
FROMTOLOAD
(INPUT)(OUTPUT)CAPACITANCE
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
or
or
or
or
or
or
CL = 15 pF80*125*70*70
CL = 50 pF50754545
p
=
L
p
= 15
L
p
=
L
p
=
L
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROMTOLOAD
(INPUT)(OUTPUT)CAPACITANCE
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
or
or
or
or
or
CL = 15 pF130*170*110*110
CL = 50 pF901157575
p
= 15
L
p
= 15
L
p
=
L
p
= 50
L
TA = 25°CSN54AHC74SN74AHC74
MINTYPMAXMINMAXMINMAX
7.6*12.3*1*14.5*114.5
7.6*12.3*1*14.5*114.5
6.7*11.9*1*14*114
6.7*11.9*1*14*114
10.115.8118118
10.115.8118118
9.215.4117.5117.5
9.215.4117.5117.5
TA = 25°CSN54AHC74SN74AHC74
MINTYPMAXMINMAXMINMAX
4.8*7.7*1*9*19
4.8*7.7*1*9*19
4.6*7.3*1*8.5*18.5
4.6*7.3*1*8.5*18.5
6.39.7111111
6.39.7111111
6.19.3110.5110.5
6.19.3110.5110.5
z
z
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage3.5V
Low-level dynamic input voltage1.5V
operating characteristics, V
C
Power dissipation capacitanceNo load,f = 1 MHz32pF
pd
= 5 V, C
CC
CC
PARAMETERTEST CONDITIONSTYPUNIT
= 50 pF, TA = 25°C (see Note 4)
L
OL
OL
OH
= 5 V, TA = 25°C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AHC74
MINMAX
0.8V
–0.8V
4.7V
5
SN54AHC74, SN74AHC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
V
CC
GND
Open
TESTS1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
w
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
50% V
50% V
VOLTAGE WAVEFORMS
50% V
CC
CC
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
CC
0 V
t
PHL
V
t
PLH
CC
CC
OH
V
OL
V
OH
V
OL
50% V
50% V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
50% V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
50% V
50% V
CC
CC
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CC
t
50% V
50% V
h
CC
CC
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈V
V
OL
V
OH
≈0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. T esting and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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