Texas Instruments SN74AHC74D, SN74AHC74DBLE, SN74AHC74DBR, SN74AHC74DGVR, SN74AHC74DR Datasheet

SN54AHC74, SN74AHC74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Operating Range 2-V to 5.5-V V

D

Latch-Up Performance Exceeds 250 mA Per

CC

JESD 17

D

ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs

description

The ’AHC74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

SN54AHC74 ...J OR W PACKAGE

SN74AHC74 . . . D, DB, DGV, N, OR PW PACKAGE

1CLR

1CLK 1PRE

SN54AHC74 . . . FK PACKAGE

1CLK

NC

1PRE

NC

1Q

NC – No internal connection

(TOP VIEW)

1

1D

2 3 4

1Q

5 6

1Q

GND

7

(TOP VIEW)

1D

3212019

4 5 6 7 8

910111213

1Q

1CLR

NC

GND

14 13 12 11 10

9 8

CC

V

2Q

V

CC

2CLR 2D 2CLK 2PRE 2Q 2Q

2CLR

18 17 16 15 14

2Q

2D NC 2CLK NC 2PRE

The SN54AHC74 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74AHC74 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright  2000, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

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1

SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000

FUNCTION TABLE

(each flip-flop)

INPUTS

PRE CLR CLK D Q Q

L H X X H L

H LXXLH

L LXXH†H H H ↑ HHL H H ↑ LLH H H L X Q

†

This configuration is nonstable; that is, it does not persist when PRE (high) level.

or CLR returns to its inactive

OUTPUTS

0

†

Q

0

logic symbol

‡

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.

‡

1PRE

1CLK

1D

1CLR

2PRE

2CLK

2D

2CLR

4 3 2 1

10 11 12 13

S

C1 1D R

logic diagram, each flip-flop (positive logic)

PRE

CLK

C

TG

5

1Q

6

1Q

9

2Q

8

2Q

Q

2

CLR

C

D

TG

C

TG

C

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C

TG

Q

C

UNIT

mA

∆t/∆vInput transition rise or fall rate

ns/V

SN54AHC74, SN74AHC74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V Input clamp current, I Output clamp current, I

(see Note 1) –0.5 V to V

O

(V

IK

I

OK

Continuous output current, I

< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(V

< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(V

= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

SN54AHC74 SN74AHC74

MIN MAX MIN MAX

V

V V

I

OH

I

OL

T

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5.5 2 5.5 V

CC

VCC = 2 V 1.5 1.5

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

High-level output current

Low-level output current

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

VCC = 3 V VCC = 5.5 V 3.85 3.85 VCC = 2 V 0.5 0.5 VCC = 3 V VCC = 5.5 V 1.65 1.65

VCC = 2 V –50 –50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V –8 –8 VCC = 2 V 50 50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 8 8 VCC = 3.3 V ± 0.3 V 100 100 VCC = 5 V ± 0.5 V 20 20

2.1 2.1

0.9 0.9

CC

–4 –4

4 4

0 V

CC

V

m

A

m

A

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3

SN54AHC74, SN74AHC74

PARAMETER

TEST CONDITIONS

V

UNIT

twPulse duration

ns

t

Set

CLK↑

ns

UNIT

twPulse duration

ns

t

Set

CLK↑

ns

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

CC

2 V 1.9 2 1.9 1.9

IOH = –50 mA

V

OH

IOH = –4 mA 3 V 2.58 2.48 2.48 IOH = –8 mA 4.5 V 3.94 3.8 3.8

IOL = 50 mA

V

OL

IOL = 4 mA 3 V 0.36 0.5 0.44 IOL = 8 mA 4.5 V 0.36 0.5 0.44

I

CC

C

i

* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.

VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1 VI = VCC or GND, IO = 0 5.5 V 2 20 20 VI = VCC or GND 5 V 2 10 10 pF

3 V 2.9 3 2.9 2.9

4.5 V 4.4 4.5 4.4 4.4

2 V 0.1 0.1 0.1 3 V 0.1 0.1 0.1

4.5 V 0.1 0.1 0.1

TA = 25°C SN54AHC74 SN74AHC74

MIN TYP MAX MIN MAX MIN MAX

V

m

A

m

A

timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

TA = 25°C SN54AHC74 SN74AHC74 MIN MAX MIN MAX MIN MAX

PRE or CLR low 6 7 7 CLK 6 7 7

su

t

h

up time before

Hold time, data after CLK↑ 0.5 0.5 0.5 ns

Data 6 7 7 PRE or CLR inactive 5 5 5

timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

TA = 25°C SN54AHC74 SN74AHC74 MIN MAX MIN MAX MIN MAX

PRE or CLR low 5 5 5 CLK 5 5 5

su

t

h

up time before

Hold time, data after CLK↑ 0.5 0.5 0.5 ns

Data 5 5 5 PRE or CLR inactive 3 3 3

4

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PARAMETER

UNIT

f

MH

PRE

CLR

Q

C

15 pF

ns

CLK

Q

C

pF

ns

PRE

CLR

Q

C

50 pF

ns

CLK

Q

C

50 pF

ns

PARAMETER

UNIT

f

MH

PRE

CLR

Q

C

pF

ns

CLK

Q

C

pF

ns

PRE

CLR

Q

C

50 pF

ns

CLK

Q or Q

C

pF

ns

PARAMETER

UNIT

SN54AHC74, SN74AHC74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000

switching characteristics over recommended operating free-air temperature range, V

= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

max

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

or

CL = 15 pF 80* 125* 70* 70 CL = 50 pF 50 75 45 45

p

=

L

p

= 15

L

p

=

L

p

=

L

switching characteristics over recommended operating free-air temperature range,

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

max

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

or

CL = 15 pF 130* 170* 110* 110 CL = 50 pF 90 115 75 75

p

= 15

L

p

= 15

L

p

=

L

p

= 50

L

TA = 25°C SN54AHC74 SN74AHC74

MIN TYP MAX MIN MAX MIN MAX

7.6* 12.3* 1* 14.5* 1 14.5

6.7* 11.9* 1* 14* 1 14

10.1 15.8 1 18 1 18

9.2 15.4 1 17.5 1 17.5

TA = 25°C SN54AHC74 SN74AHC74

MIN TYP MAX MIN MAX MIN MAX

4.8* 7.7* 1* 9* 1 9

4.6* 7.3* 1* 8.5* 1 8.5

6.3 9.7 1 11 1 11

6.1 9.3 1 10.5 1 10.5

z

noise characteristics, V

V

OL(P)

V

OL(V)

V

OH(V)

V

IH(D)

V

IL(D)

NOTE 4: Characteristics are for surface-mount packages only.

Quiet output, maximum dynamic V Quiet output, minimum dynamic V Quiet output, minimum dynamic V High-level dynamic input voltage 3.5 V Low-level dynamic input voltage 1.5 V

operating characteristics, V

C

Power dissipation capacitance No load, f = 1 MHz 32 pF

pd

= 5 V, C

CC

PARAMETER TEST CONDITIONS TYP UNIT

= 50 pF, TA = 25°C (see Note 4)

L

OL OL OH

= 5 V, TA = 25°C

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SN74AHC74

MIN MAX

0.8 V

–0.8 V

4.7 V

5

SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

(see Note A)

Test Point

C

L

From Output

Under Test

(see Note A)

C

L

RL = 1 kΩ

S1

V

CC

GND

Open

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open Drain

Open

V

CC

GND V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Input

t

PLH

In-Phase

Output

t

PHL

Out-of-Phase

Output

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

t

w

50% V

CC

VOLTAGE WAVEFORMS

PULSE DURATION

50% V

CC

50% V

VOLTAGE WAVEFORMS

50% V

CC

3-STATE AND OPEN-DRAIN OUTPUTS

50% V

LOAD CIRCUIT FOR

V

CC

0 V

V

CC

0 V

t

PHL

V

t

PLH

CC

OH

V

OL

V

OH

V

OL

50% V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

50% V

t

su

50% V

CC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

50% V

CC

t

PZL

50% V

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

CC

t

50% V

h

CC

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

V

CC

0 V

V

CC

0 V

V

CC

0 V

≈V

V

OL

V

OH

≈0 V

CC

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

6

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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Texas Instruments SN74AHC74D, SN74AHC74DBLE, SN74AHC74DBR, SN74AHC74DGVR, SN74AHC74DR Datasheet

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