Datasheet SN74AHC595PWR, SN74AHC595D, SN74AHC595DBR, SN74AHC595DR, SN74AHC595N Datasheet (Texas Instruments)
SN54AHC595, SN74AHC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS373E – MAY 1997 – REVISED JANUAR Y 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Operating Range 2-V to 5.5-V V
D
8-Bit Serial-In, Parallel-Out Shift
D
Shift Register Has Direct Clear
D
Latch-Up Performance Exceeds 250 mA Per
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
description
The ’AHC595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
both the shift and storage registers. The shift
register has a direct overriding clear (SRCLR
input, serial (SER) input, and a serial output for
cascading. When the output-enable (OE
high, all outputs, except QH′, are in the
high-impedance state.
) input is
SN54AHC595 ...J OR W PACKAGE
SN74AHC595 . . . D, DB, N, OR PW PACKAGE
SN54AHC595 . . . FK PACKAGE
Q
D
Q
E
NC
Q
F
Q
G
)
NC – No internal connection
(TOP VIEW)
Q
1
B
Q
2
C
Q
3
D
Q
4
E
5
Q
F
6
Q
G
7
Q
H
GND
8
(TOP VIEW)
CQB
Q
3212019
4
5
6
7
8
910111213
H
Q
NC
GND
NC
16
15
14
13
12
11
10
9
VCCQ
′
H
Q
V
CC
Q
A
SER
OE
RCLK
SRCLK
SRCLR
Q
H′
A
SER
18
OE
17
NC
16
RCLK
15
14
SRCLK
SRCLR
Both the shift-register clock (SRCLK) and storage-register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
The SN54AHC595 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AHC595 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54AHC595, SN74AHC595
FUNCTION
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS373E – MAY 1997 – REVISED JANUAR Y 2000
INPUTS
SER SRCLK SRCLR RCLK OE
X X X X H Outputs QA–QH are disabled.
X X X X L Outputs QA–QH are enabled.
X X L X X Shift register is cleared.
L ↑ H X X
H ↑ H X X
X ↓ H X X Shift-register state is not changed.
X XX↑ X Shift-register data is stored into the storage register.
X X X ↓ X Storage-register state is not changed.
FUNCTION TABLE
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
†
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
EN3
R
1D
C2
SRG8
C1/
2D
2D
15
3
3
Q
A
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
7
Q
H
9
Q
H′
2
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logic diagram (positive logic)
13
OE
SER
12
10
11
14
RCLK
SRCLR
SRCLK
1D
R
C1
SN54AHC595, SN74AHC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS373E – MAY 1997 – REVISED JANUAR Y 2000
Q
3D
C3
Q
15
Q
A
2D
R
2D
R
2D
R
2D
R
2D
R
2D
R
C2
C2
C2
C2
C2
C2
Q
Q
Q
Q
Q
Q
3D
3D
3D
3D
3D
3D
C3
C3
C3
C3
C3
C3
Q
Q
Q
Q
Q
Q
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
2D
C2
R
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Q
3D
C3
7
Q
Q
H
9
Q
H′
3
SN54AHC595, SN74AHC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS373E – MAY 1997 – REVISED JANUAR Y 2000
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H’
4
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UNIT
mA
mA
∆t/∆vInput transition rise or fall rate
ns/V
SN54AHC595, SN74AHC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS373E – MAY 1997 – REVISED JANUAR Y 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, I
Output clamp current, I
(see Note 1) –0.5 V to V
O
(V
IK
I
OK
Continuous output current, I
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AHC595 SN74AHC595
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 3 V
VCC = 5.5 V 3.85 3.85
VCC = 2 V 0.5 0.5
VCC = 3 V
VCC = 5.5 V 1.65 1.65
VCC = 2 V –50 –50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V –8 –8
VCC = 2 V 50 50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 8 8
VCC = 3.3 V ± 0.3 V 100 100
VCC = 5 V ± 0.5 V 20 20
2.1 2.1
0.9 0.9
CC
–4 –4
4 4
0 V
CC
V
V
V
m
A
m
A
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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5
SN54AHC595, SN74AHC595
PARAMETER
TEST CONDITIONS
V
UNIT
OH
OL
UNIT
t
Set
ns
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS373E – MAY 1997 – REVISED JANUAR Y 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
2 V 1.9 2 1.9 1.9
IOH = –50 mA
V
OH
IOH = –4 mA
IOH = –8 mA
IOL = 50 mA
V
OL
IOL = 4 mA
IOL = 8 mA
I
I
I
OZ
I
CC
C
i
C
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
VI = VCC or GND, VO = VCC or GND,
OE
= VIH or V
VI = VCC or GND, IO = 0 5.5 V 4 40 40
VI = VCC or GND 5 V 3 10 10 pF
VO = VCC or GND 5 V 5.5 pF
IL
3 V 2.9 3 2.9 2.9
4.5 V 4.4 4.5 4.4 4.4
3 V 2.58 2.48 2.48
4.5 V 3.94 3.8 3.8
2 V 0.1 0.1 0.1
3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
3 V 0.36 0.5 0.44
4.5 V 0.36 0.5 0.44
5.5 V ±0.25 ±2.5 ±2.5
TA = 25°C SN54AHC595 SN74AHC595
MIN TYP MAX MIN MAX MIN MAX
V
V
m
A
m
A
m
A
timing requirements over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C SN54AHC595 SN74AHC595
MIN MAX MIN MAX MIN MAX
SRCLK high or low 5 5 5
t
Pulse duration
w
su
t
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together , in which case the shift
register is one clock pulse ahead of the storage register.
up time
Hold time SER after SRCLK↑ 1.5 1.5 1.5 ns
RCLK high or low
SRCLR low 5 5 5
SER before SRCLK↑ 3.5 3.5 3.5
SRCLK↑ before RCLK↑
low before RCLK↑ 8 9 9
SRCLR
SRCLR high (inactive) before SRCLK↑ 3 3 3
†
5 5 5
8 8.5 8.5
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
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UNIT
t
Set
ns
PARAMETER
UNIT
f
MH
RCLK
Q
Q
C
pF
ns
SRCLK
Q
C
pF
ns
OE
Q
Q
C
pF
ns
RCLK
Q
Q
C
pF
ns
SRCLK
Q
C
pF
ns
OE
Q
Q
C
pF
ns
OE
Q
Q
C
pF
ns
SN54AHC595, SN74AHC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS373E – MAY 1997 – REVISED JANUAR Y 2000
timing requirements over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C SN54AHC595 SN74AHC595
MIN MAX MIN MAX MIN MAX
SRCLK high or low 5 5 5
t
Pulse duration
w
su
t
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together , in which case the shift
register is one clock pulse ahead of the storage register.
up time
Hold time SER after SRCLK↑ 2 2 2 ns
RCLK high or low
SRCLR low 5 5 5
SER before SRCLK↑ 3 3 3
SRCLK↑ before RCLK↑
low before RCLK↑ 5 5 5
SRCLR
SRCLR high (inactive) before SRCLK↑ 2.5 2.5 2.5
†
5 5 5
5 5 5
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SRCLR Q
SRCLR Q
–
A
H
H′
H′
–
A
H
–
A
H
H′
H′
–
A
H
–
A
H
CL = 15 pF 80* 120* 70* 70
CL = 50 pF 55 105 50 50
p
= 15
L
p
= 15
L
CL = 15 pF 6.2* 12.8* 1* 13.7* 1 13.7 ns
p
= 15
L
p
= 50
L
p
= 50
L
CL = 50 pF 9 16.3 1 17.2 1 17.2 ns
p
= 50
L
p
= 50
L
TA = 25°C SN54AHC595 SN74AHC595
MIN TYP MAX MIN MAX MIN MAX
6* 11.9* 1* 13.5* 1 13.5
6* 11.9* 1* 13.5* 1 13.5
6.6* 13* 1* 15* 1 15
6.6* 13* 1* 15* 1 15
6* 11.5* 1* 13.5* 1 13.5
7.8* 11.5* 1* 13.5* 1 13.5
7.9 15.4 1 17 1 17
7.9 15.4 1 17 1 17
9.2 16.5 1 18.5 1 18.5
9.2 16.5 1 18.5 1 18.5
7.8 15 1 17 1 17
9.6 15 1 17 1 17
8.1 15.7 1 16.2 1 16.2
9.3 15.7 1 16.2 1 16.2
ns
z
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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SN54AHC595, SN74AHC595
PARAMETER
UNIT
f
MH
RCLK
Q
Q
C
15 pF
ns
SRCLK
Q
C
pF
ns
OE
Q
Q
C
15 pF
ns
RCLK
Q
Q
C
pF
ns
SRCLK
Q
C
50 pF
ns
OE
Q
Q
C
pF
ns
OE
Q
Q
C
pF
ns
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS373E – MAY 1997 – REVISED JANUAR Y 2000
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SRCLR Q
SRCLR Q
–
A
H
H′
H′
–
A
H
–
A
H
H′
H′
–
A
H
–
A
H
CL = 15 pF 135* 170* 115* 115
CL = 50 pF 95 140 85 85
p
=
L
p
= 15
L
CL = 15 pF 4.5* 8* 1* 9.1* 1 9.1 ns
p
=
L
p
= 50
L
p
=
L
CL = 50 pF 6.4 10 1 11.1 1 11.1 ns
p
= 50
L
p
= 50
L
TA = 25°C SN54AHC595 SN74AHC595
MIN TYP MAX MIN MAX MIN MAX
4.3* 7.4* 1* 8.5* 1 8.5
4.3* 7.4* 1* 8.5* 1 8.5
4.5* 8.2* 1* 9.4* 1 9.4
4.5* 8.2* 1* 9.4* 1 9.4
4.3* 8.6* 1* 10* 1 10
5.4* 8.6* 1* 10* 1 10
5.6 9.4 1 10.5 1 10.5
5.6 9.4 1 10.5 1 10.5
6.4 10.2 1 11.4 1 11.4
6.4 10.2 1 11.4 1 11.4
5.7 10.6 1 12 1 12
6.8 10.6 1 12 1 12
3.5 10.3 1 11 1 11
3.4 10.3 1 11 1 11
z
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 25.2 pF
pd
= 5 V, T
CC
PARAMETER TEST CONDITIONS TYP UNIT
= 25°C
A
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
C
SN54AHC595, SN74AHC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS373E – MAY 1997 – REVISED JANUAR Y 2000
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
w
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
50% V
50% V
VOLTAGE WAVEFORMS
50% V
CC
CC
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
CC
t
PHL
50% V
t
PLH
50% V
CC
CC
0 V
V
V
V
V
OH
OL
OH
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
50% V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
50% V
50% V
CC
CC
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CC
50% V
50% V
t
h
CC
CC
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈V
V
OL
V
OH
≈0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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9
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TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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