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SN74AHC594NSR

Datasheet SN74AHC594DBR, SN74AHC594DR, SN74AHC594N, SN74AHC594NSR, SN74AHC594PWR Datasheet (Texas Instruments)

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SN54AHC594, SN74AHC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS423C – JUNE 1998 – REVISED JANUARY 2000
D
(Enhanced-Performance
Implanted CMOS) Process
D
Operating Range 2-V to 5.5-V V
D
8-Bit Serial-In, Parallel-Out Shift
CC
Registers With Storage
D
Independent Direct Overriding Clears on Shift and Storage Registers
D
Independent Clocks for Shift and Storage Registers
D
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
D
ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
D
Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
description
The ’AHC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clear (SRCLR, RCLR) inputs are provided on the shift and storage registers. A serial (Q purposes.
) output is provided for cascading
H′
SN54AHC594 ...J OR W PACKAGE
SN74AHC594 . . . D, DB, N, OR PW PACKAGE
SN54AHC594 . . . FK PACKAGE
Q
D
Q
E
NC
Q
F
Q
G
NC – No internal connection
(TOP VIEW)
Q
1
B
Q
2
C
Q
3
D
Q
4
E
5
Q
F
6
Q
G
7
Q
H
GND
8
(TOP VIEW)
CQB
Q
3212019
4 5 6 7 8
910111213
H
Q
NC
NC
GND
16 15 14 13 12 11 10
9
VCCQ
′
H
Q
V
CC
Q
A
SER RCLR RCLK SRCLK SRCLR Q
H′
A
SER
18
RCLR
17
NC
16
RCLK
15 14
SRCLK
SRCLR
The shift register (SRCLK) and storage register (RCLK) clocks are positive-edge triggered. If the clocks are tied together, the shift register always is one clock pulse ahead of the storage register.
The SN54AHC594 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74AHC594 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright  2000, Texas Instruments Incorporated
1
SN54AHC594, SN74AHC594
FUNCTION
8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
SCLS423C – JUNE 1998 – REVISED JANUARY 2000
INPUTS
SER SRCLK SRCLR RCLK RCLR
X X L X X Shift register is cleared. L ↑ H X X
H ↑ H X X L ↓ H X X Shift register state is not changed.
X X X X L Storage register is cleared. X XX↑ H Shift register data is stored in the storage register. X X X ↓ H Storage register state is not changed.
FUNCTION TABLE
First stage of shift register goes low. Other stages store the data of previous stage, respectively.
First stage of shift register goes high. Other stages store the data of previous stage, respectively.
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
†
SER
13 12
10 11
14
RCLR
RCLK C2
SRCLR
SRCLK C1/
R3
R
1D
SRG8
2D
2D
15
3
3
Q
A
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
7
Q
H
9
Q
H′
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54AHC594, SN74AHC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS423C – JUNE 1998 – REVISED JANUARY 2000
RCLR
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14 15
1D
R
2D
R
2D
R
2D
R
Q
C1
Q
C2
Q
C2
Q
C2
R 3D
R 3D
R 3D
R 3D
Q
C3
Q
C3
Q
C3
Q
C3
Q
A
1
Q
B
2
Q
C
3
Q
D
2D
R
2D
R
2D
R
2D
R
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
C2
C2
C2
C2
Q
Q
Q
Q
R 3D
R 3D
R 3D
R 3D
Q
C3
Q
C3
Q
C3
Q
C3
4
Q
E
5
Q
F
6
Q
G
7
Q
H
9
Q
H′
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54AHC594, SN74AHC594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
SCLS423C – JUNE 1998 – REVISED JANUARY 2000
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H’
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
mA
mA
Dt/DvInput transition rise or fall rate
ns/V
SN54AHC594, SN74AHC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS423C – JUNE 1998 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AHC594 SN74AHC594
MIN MAX MIN MAX
V
V
V
V V
I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 3 V VCC = 5.5 V 3.85 3.85 VCC = 2 V 0.5 0.5 VCC = 3 V VCC = 5.5 V 1.65 1.65
VCC = 2 V –50 –50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V –8 –8 VCC = 2 V 50 50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 8 8 VCC = 3.3 V ± 0.3 V 100 100 VCC = 5 V ± 0.5 V 20 20
2.1 2.1
0.9 0.9
CC
–4 –4
4 4
0 V
CC
V
V
V
m
A
m
A
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54AHC594, SN74AHC594
PARAMETER
TEST CONDITIONS
V
UNIT
4.5 V
4.5 V
UNIT
twPulse duration
ns
8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
SCLS423C – JUNE 1998 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
CC
2 V 1.9 2 1.9 1.9
IOH = –50 mA
V
OH
V
OL
I
I
I
CC
C
i
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
IOH = –4 mA QH′,IOH = –4 mA QA–QH, IOH = –8 mA
IOL = 50 mA
IOL = 4 mA QH′, IOL = 4 mA QA–QH, IOL = 8 mA
VI = VCC or GND 0 V to 5.5 V ± 0.1 ±1* ± 1 VI = VCC or GND, IO = 0 5.5 V 4 40 40 VI = VCC or GND 5 V 2 10 10 pF
3 V 2.9 3 2.9 2.9
4.5 V 4.4 4.5 4.4 4.4 3 V 2.58 2.48 2.48
2 V 0.1 0.1 0.1 3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1 3 V 0.36 0.5 0.44
TA = 25°C SN54AHC594 SN74AHC594
MIN TYP MAX MIN MAX MIN MAX
3.94 3.8 3.8
3.94 3.8 3.8
0.36 0.5 0.44
0.36 0.5 0.44
V
V
m
A
m
A
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C SN54AHC594 SN74AHC594 MIN MAX MIN MAX MIN MAX
RCLK or SRCLK high or low 5.5 5.5 5.5 RCLR or SRCLR low 5 5 5 SER before SRCLK↑ 3.5 3.5 3.5 SRCLK↑ before RCLK↑
t
Setup time
su
t
Hold time SER after SRCLK↑ 1.5 1.5 1.5 ns
h
†
This setup time allows the storage register to receive stable data from the shift register . The clocks can be tied together , in which case the shift register is one clock pulse ahead of the storage register.
SRCLR low before RCLK↑ 8 9 9 SRCLR high (inactive) before SRCLK↑ 4.2 4.8 4.8 RCLR high (inactive) before RCLK↑ 4.6 5.3 5.3
†
8 8.5 8.5
ns
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
6
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UNIT
twPulse duration
ns
PARAMETER
UNIT
f
MH
RCLK
Q
Q
C
pF
ns
SRCLK
Q
C
pF
ns
RCLK
Q
Q
C
pF
ns
SRCLK
Q
C
pF
ns
SN54AHC594, SN74AHC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS423C – JUNE 1998 – REVISED JANUARY 2000
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C SN54AHC594 SN74AHC594 MIN MAX MIN MAX MIN MAX
RCLK or SRCLK high or low 5 5 5 RCLR or SRCLR low 5.2 5.2 5.2 SER before SRCLK↑ 3 3 3 SRCLK↑ before RCLK↑
t
Setup time
su
t
Hold time SER after SRCLK↑ 2 2 2 ns
h
†
This setup time allows the storage register to receive stable data from the shift register . The clocks can be tied together , in which case the shift register is one clock pulse ahead of the storage register.
SRCLR low before RCLK↑ 5 5 5 SRCLR high (inactive) before SRCLK↑ 2.9 3.3 3.3 RCLR high (inactive) before RCLK↑ 3.2 3.7 3.7
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
RCLR QA–Q
SRCLR Q
RCLR QA–Q
SRCLR Q
–
A
H
H′
H
H′
–
A
H
H′
H
H′
†
MIN TYP MAX MIN MAX MIN MAX
CL = 15 pF 80* 120* 70* 70 CL = 50 pF 55 105 50 50
p
= 15
L
p
= 15
L
CL = 15 pF 6* 9.8* 1* 10.6* 1 10.6 ns CL = 15 pF 5.6* 9.2* 1* 10* 1 10 ns
p
= 50
L
p
= 50
L
CL = 50 pF 9.1 13.1 1 14.4 1 14.4 ns CL = 50 pF 8.5 12.4 1 14 1 14 ns
5 5 5
ns
TA = 25°C SN54AHC594 SN74AHC594
4.6* 8* 1* 8.5* 1 8.5
4.9* 8.2* 1* 8.8* 1 8.8
5.4* 9.1* 1* 9.7* 1 9.7
5.5* 9.2* 1* 9.9* 1 9.9
6.9 10.5 1 11.1 1 11.1
8.1 11.9 1 13.1 1 13.1
7.7 11.7 1 12.4 1 12.4
8.4 12.5 1 13.9 1 13.9
z
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54AHC594, SN74AHC594
PARAMETER
UNIT
f
MH
RCLK
Q
Q
C
15 pF
ns
SRCLK
Q
C
pF
ns
RCLK
Q
Q
C
pF
ns
SRCLK
Q
C
pF
ns
PARAMETER
UNIT
8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
SCLS423C – JUNE 1998 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range, V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
RCLR QA–Q
SRCLR Q
RCLR QA–Q
SRCLR Q
–
A
H
H′
H
H′
–
A
H
H′
H
H′
CL = 15 pF 135* 170* 115* 115 CL = 50 pF 120 140 95 95
p
=
L
p
= 15
L
CL = 15 pF 4.5* 7.6* 1* 8.2* 1 8.2 ns CL = 15 pF 4.1* 7.1* 1* 7.6* 1 7.6 ns
p
= 50
L
p
= 50
L
CL = 50 pF 6.6 10 1 10.7 1 10.7 ns CL = 50 pF 6 9.2 1 10.1 1 10.1 ns
TA = 25°C SN54AHC594 SN74AHC594
MIN TYP MAX MIN MAX MIN MAX
3.3* 6.2* 1* 6.5* 1 6.5
3.7* 6.5* 1* 6.9* 1 6.9
3.7* 6.8* 1* 7.2* 1 7.2
4.1* 7.2* 1* 7.6* 1 7.6
4.9 7.8 1 8.3 1 8.3
5.8 8.9 1 9.7 1 9.7
5.5 8.6 1 9.1 1 9.1 6 9.2 1 10.1 1 10.1
z
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V Quiet output, minimum dynamic V Quiet output, minimum dynamic V High-level dynamic input voltage 3.5 V Low-level dynamic input voltage 1.5 V
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 112 pF
pd
= 5 V, CL = 50 pF, TA = 25°C (see Note 4)
CC
OL OL OH
= 5 V, T
CC
PARAMETER TEST CONDITIONS TYP UNIT
= 25°C
A
SN74AHC594
MIN TYP MAX
1 V
–0.6 V
3.8 V
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54AHC594, SN74AHC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS423C – JUNE 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
Test Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
VOLTAGE WAVEFORMS
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
w
50% V
CC
PULSE DURATION
50% V
CC
50% V
50% V
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
50% V
CC
CC
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
CC
t
PHL
50% V
t
PLH
50% V
CC
CC
0 V
V
V
V
V
OH
OL
OH
OL
Timing Input
Waveform 1
(see Note B)
Waveform 2
(see Note B)
Data Input
Output
Control
Output
S1 at V
CC
Output
S1 at GND
50% V
CC
t
CC
CC
h
50% V
50% V
VOL + 0.3 V
VOH – 0.3 V
CC
t
t
CC
PLZ
PHZ
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈V
V
OL
V
OH
≈0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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