Texas Instruments SN74AHC573DBLE, SN74AHC573DBR, SN74AHC573DGVR, SN74AHC573DW, SN74AHC573DWR Datasheet
...
SN54AHC573, SN74AHC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS242I – OCTOBER 1995 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Operating Range 2-V to 5.5-V V
D
3-State Outputs Directly Drive Bus Lines
D
Latch-Up Performance Exceeds 250 mA Per
CC
JESD 17
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
description
The ’AHC573 devices are octal transparent
D-type latches designed for 2-V to 5.5-V V
operation.
When the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is
low, the Q outputs are latched at the logic levels
of the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
CC
SN74AHC573 . . . DB, DGV, DW, N, OR PW PACKAGE
SN54AHC573 ...J OR W PACKAGE
(TOP VIEW)
LE
20
19
18
17
16
15
14
13
12
11
V
8Q
CC
V
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
18
17
16
15
14
7Q 1Q
CC
2Q
3Q
4Q
5Q
6Q
OE
1
1D
2
2D
3
3D
4
4D
5
5D
6
6D
7
7D
8
8D
9
GND
SN54AHC573 . . . FK PACKAGE
3D
4D
5D
6D
7D
10
(TOP VIEW)
2D1DOE
3212019
4
5
6
7
8
910111213
8D
GND
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHC573 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AHC573 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54AHC573, SN74AHC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS242I – OCTOBER 1995 – REVISED JANUARY 2000
FUNCTION TABLE
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
(each latch)
OUTPUT
Q
0
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
1
11
2
3
4
5
6
7
8
9
EN
C1
1D
logic diagram (positive logic)
1
OE
11
LE
C1
1D
1D
2
19
18
17
16
15
14
13
12
19
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1Q
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
mA
mA
∆t/∆vInput transition rise or fall rate
ns/V
SN54AHC573, SN74AHC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS242I – OCTOBER 1995 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, I
Output clamp current, I
(see Note 1) –0.5 V to V
O
(V
IK
I
OK
Continuous output current, I
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AHC573 SN74AHC573
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 3 V
VCC = 5.5 V 3.85 3.85
VCC = 2 V 0.5 0.5
VCC = 3 V
VCC = 5.5 V 1.65 1.65
VCC = 2 V –50 –50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V –8 –8
VCC = 2 V 50 50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 8 8
VCC = 3.3 V ± 0.3 V 100 100
VCC = 5 V ± 0.5 V 20 20
2.1 2.1
0.9 0.9
CC
–4 –4
4 4
0 V
CC
V
V
V
m
A
m
A
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54AHC573, SN74AHC573
PARAMETER
TEST CONDITIONS
V
UNIT
OH
OL
UNIT
UNIT
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS242I – OCTOBER 1995 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
2 V 1.9 2 1.9 1.9
IOH = –50 mA
V
OH
IOH = –4 mA
IOH = –8 mA
IOL = 50 mA
V
OL
IOL = 4 mA
IOL = 8 mA
I
I
I
OZ
I
CC
C
i
C
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
VI = VIL or VIH, VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5
VI = VCC or GND, IO = 0 5.5 V 4 40 40
VI = VCC or GND 5 V 2.5 10 10 pF
VO = VCC or GND 5 V 3.5 pF
3 V 2.9 3 2.9 2.9
4.5 V 4.4 4.5 4.4 4.4
3 V 2.58 2.48 2.48
4.5 V 3.94 3.8 3.8
2 V 0.1 0.1 0.1
3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
3 V 0.36 0.5 0.44
4.5 V 0.36 0.5 0.44
TA = 25°C SN54AHC573 SN74AHC573
MIN TYP MAX MIN MAX MIN MAX
V
V
m
A
m
A
m
A
timing requirements over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
TA = 25°C SN54AHC573 SN74AHC573
MIN MAX MIN MAX MIN MAX
t
Pulse duration, LE high 5 5 5 ns
w
t
Setup time, data before LE↓
su
t
Hold time, data after LE↓ 1.5 1.5 1.5 ns
h
3.5 3.5 3.5 ns
timing requirements over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
TA = 25°C SN54AHC573 SN74AHC573
MIN MAX MIN MAX MIN MAX
t
Pulse duration, LE high 5 5 5 ns
w
t
Setup time, data before LE↓
su
t
Hold time, data after LE↓ 1.5 1.5 1.5 ns
h
3.5 3.5 3.5 ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
UNIT
D
Q
C
15 pF
ns
LE
Q
C
15 pF
ns
OE
Q
C
pF
ns
OE
Q
C
15 pF
ns
D
Q
C
50 pF
ns
LE
Q
C
pF
ns
OE
Q
C
pF
ns
OE
Q
C
50 pF
ns
PARAMETER
UNIT
D
Q
C
pF
ns
LE
Q
C
pF
ns
OE
Q
C
15 pF
ns
OE
Q
C
pF
ns
D
Q
C
pF
ns
LE
Q
C
50 pF
ns
OE
Q
C
pF
ns
OE
Q
C
pF
ns
SN54AHC573, SN74AHC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS242I – OCTOBER 1995 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
∗
On products compliant to MIL-PRF-38535, this parameter is not production tested.
∗∗
On products compliant to MIL-PRF-38535, this parameter does not apply.
CL = 50 pF 1.5** 1.5 ns
=
L
=
L
= 15
L
=
L
=
L
= 50
L
= 50
L
=
L
p
p
p
p
p
p
p
p
TA = 25°C SN54AHC573 SN74AHC573
MIN TYP MAX MIN MAX MIN MAX
7* 11* 1* 13* 1 13
7* 11* 1* 13* 1 13
7.6* 11.9* 1* 14* 1 14
7.6* 11.9* 1* 14* 1 14
7.3* 11.5* 1* 13.5* 1 13.5
7.3* 11.5* 1* 13.5* 1 13.5
8.3* 11* 1* 13* 1 13
8.3* 11* 1* 13* 1 13
9.5 14.5 1 16.5 1 16.5
9.5 14.5 1 16.5 1 16.5
10.1 15.4 1 17.5 1 17.5
10.1 15.4 1 17.5 1 17.5
9.8 15 1 17 1 17
9.8 15 1 17 1 17
10.7 14.5 1 16.5 1 16.5
10.7 14.5 1 16.5 1 16.5
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
∗
On products compliant to MIL-PRF-38535, this parameter is not production tested.
∗∗
On products compliant to MIL-PRF-38535, this parameter does not apply.
CL = 50 pF 1** 1 ns
= 15
L
= 15
L
=
L
= 15
L
= 50
L
=
L
= 50
L
= 50
L
p
p
p
p
p
p
p
p
TA = 25°C SN54AHC573 SN74AHC573
MIN TYP MAX MIN MAX MIN MAX
4.5* 6.8* 1 8* 1 8
4.5* 6.8* 1 8* 1 8
5* 7.7* 1 9* 1 9
5* 7.7* 1 9* 1 9
5.2* 7.7* 1 9* 1 9
5.2* 7.7* 1 9* 1 9
5.2* 7.7* 1 9* 1 9
5.2* 7.7* 1 9* 1 9
6 8.8 1 10 1 10
6 8.8 1 10 1 10
6.5 9.7 1 11 1 11
6.5 9.7 1 11 1 11
6.7 9.7 1 11 1 11
6.7 9.7 1 11 1 11
6.7 9.7 1 11 1 11
6.7 9.7 1 11 1 11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54AHC573, SN74AHC573
PARAMETER
UNIT
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS242I – OCTOBER 1995 – REVISED JANUARY 2000
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 3.5 V
Low-level dynamic input voltage 1.5 V
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 16 pF
pd
= 5 V, CL = 50 pF, TA = 25°C (see Note 4)
CC
OL
OL
OH
= 5 V, TA = 25°C
CC
PARAMETER TEST CONDITIONS TYP UNIT
SN74AHC573
MIN MAX
1 V
–0.8 V
4 V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54AHC573, SN74AHC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS242I – OCTOBER 1995 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
w
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
50% V
50% V
VOLTAGE WAVEFORMS
50% V
CC
CC
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
CC
t
PHL
50% V
t
PLH
50% V
CC
CC
0 V
V
V
V
V
OH
OL
OH
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
50% V
CC
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
50% V
50% V
CC
CC
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
h
50% V
50% V
VOL + 0.3 V
VOH – 0.3 V
CC
t
t
CC
PLZ
PHZ
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈V
V
OL
V
OH
≈0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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7
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