SN74AHC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCLS323G – MARCH 1996 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Operating Range 2-V to 5.5-V V
D
Latch-Up Performance Exceeds 250 mA Per
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per
DBV OR DCK PACKAGE
(TOP VIEW)
V
5
Y
4
GND
A
1
B
2
3
CC
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline Transistor (DBV, DCK)
Packages
description
The SN74AHC1G86 is a single 2-input exclusive-OR gate. The device performs the Boolean function Y = A ⊕ B
or Y = AB + AB in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
The SN74AHC1G86 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
A B
L L L
L HH
H LH
H H L
OUTPUT
Y
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
†
1
A
2
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
=1
4
Y
Copyright 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN74AHC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCLS323G – MARCH 1996 – REVISED JANUARY 2000
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative
logic symbols.
EXCLUSIVE OR
= 1
These are five equivalent exclusive-OR symbols valid for an SN74AHC1G86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
= 2k 2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
(V
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DBV package 347°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 389°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
stg
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
2
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mA
mA
∆t/∆vInput transition rise or fall rate
ns/V
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
OH
OL
SN74AHC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCLS323G – MARCH 1996 – REVISED JANUARY 2000
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
V
V
V
V
I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 V
CC
VCC = 2 V 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 3 V
VCC = 5.5 V 3.85
VCC = 2 V 0.5
VCC = 3 V
VCC = 5.5 V 1.65
VCC = 2 V –50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V –8
VCC = 2 V 50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 8
VCC = 3.3 V ± 0.3 V 100
VCC = 5 V ± 0.5 V 20
2.1
0.9
CC
–4
V
V
V
m
A
m
A
4
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
MIN TYP MAX
V
V
m
A
m
A
V
V
I
I
C
OH
OL
I
CC
i
CC
2 V 1.9 2 1.9
IOH = –50 mA
IOH = –4 mA
IOH = –8 mA
IOL = 50 mA
IOL = 4 mA
IOL = 8 mA
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1
VI = VCC or GND, IO = 0 5.5 V 1 10
VI = VCC or GND 5 V 4 10 10 pF
3 V 2.9 3 2.9
4.5 V 4.4 4.5 4.4
3 V 2.58 2.48
4.5 V 3.94 3.8
2 V 0.1 0.1
3 V 0.1 0.1
4.5 V 0.1 0.1
3 V 0.36 0.44
4.5 V 0.36 0.44
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3
SN74AHC1G86
PARAMETER
MIN
MAX
UNIT
A or B
Y
C
15 pF
ns
A or B
Y
C
50 pF
ns
PARAMETER
MIN
MAX
UNIT
A or B
Y
C
15 pF
ns
A or B
Y
C
pF
ns
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCLS323G – MARCH 1996 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PLH
t
PHL
p
=
L
p
=
L
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PLH
t
PHL
=
L
= 50
L
p
p
TA = 25°C
MIN TYP MAX
7 11 1 13
7 11 1 13
9.5 14.5 1 16.5
9.5 14.5 1 16.5
TA = 25°C
MIN TYP MAX
4.8 6.8 1 8
4.8 6.8 1 8
6.3 8.8 1 10
6.3 8.8 1 10
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 18 pF
pd
= 5 V, T
CC
PARAMETER TEST CONDITIONS TYP UNIT
= 25°C
A
4
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From Output
Under Test
(see Note A)
SN74AHC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCLS323G – MARCH 1996 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
w
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
50% V
50% V
VOLTAGE WAVEFORMS
50% V
CC
CC
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
CC
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
0 V
t
PHL
V
t
PLH
CC
V
V
CC
V
OH
OL
OH
OL
50% V
50% V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
50% V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
50% V
50% V
CC
CC
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CC
t
50% V
50% V
h
CC
CC
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈V
V
OL
V
OH
≈0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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5
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