Texas Instruments SN74AHC1G126DBVR, SN74AHC1G126DCKR Datasheet
SN74AHC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCLS379D – AUGUST 1997 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Operating Range 2-V to 5.5-V V
D
Latch-Up Performance Exceeds 250 mA Per
CC
JESD 17
D
Package Options Include Plastic
DBV OR DCK PACKAGE
(TOP VIEW)
OE
GND
1
A
2
3
V
5
Y
4
CC
Small-Outline Transistor (DBV, DCK)
Packages
description
The SN74AHC1G126 is a single bus buffer gate/line driver with 3-state output. The output is disabled when the
output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
The SN74AHC1G126 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE A
H H H
H LL
L X Z
OUTPUT
Y
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
1
2
A
EN
logic diagram (positive logic)
1
OE
24
AY
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
4
Y
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright 2000, Texas Instruments Incorporated
1
SN74AHC1G126
mA
mA
∆t/∆vInput transition rise or fall rate
ns/V
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCLS379D – AUGUST 1997 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, I
Output clamp current, I
(see Note 1) –0.5 V to V
O
(V
IK
I
OK
Continuous output current, I
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DBV package 347°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DCK package 389°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
V
V
V
V
I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 V
CC
VCC = 2 V 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 3 V
VCC = 5.5 V 3.85
VCC = 2 V 0.5
VCC = 3 V
VCC = 5.5 V 1.65
VCC = 2 V –50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V –8
VCC = 2 V 50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 8
VCC = 3.3 V ± 0.3 V 100
VCC = 5 V ± 0.5 V 20
2.1
0.9
CC
–4
V
V
V
m
A
m
A
4
2
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