SN74AHC1G02
SINGLE 2-INPUT POSITIVE-NOR GATE
SCLS342F – APRIL 1996 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Operating Range 2-V to 5.5-V V
D
Package Options Include Plastic
Small-Outline Transistor (DBV, DCK)
Packages
CC
DBV OR DCK PACKAGE
(TOP VIEW)
V
5
Y
4
GND
A
1
B
2
3
CC
description
This device contains a single 2-input NOR gate that performs the Boolean function Y = ASB or Y = A + B in
positive logic.
The SN74AHC1G02 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
logic symbol
INPUTS
A B
H X L
X HL
L L H
†
1
A
2
B
≥ 1
OUTPUT
Y
4
Y
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
A
2
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
4
Y
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
SN74AHC1G02
mA
mA
∆t/∆vInput transition rise or fall rate
ns/V
SINGLE 2-INPUT POSITIVE-NOR GATE
SCLS342F – APRIL 1996 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DBV package 347°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DCK package 389°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
V
V
V
V
I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 V
CC
VCC = 2 V 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 3 V
VCC = 5.5 V 3.85
VCC = 2 V 0.5
VCC = 3 V
VCC = 5.5 V 1.65
VCC = 2 V –50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V –8
VCC = 2 V 50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 8
VCC = 3.3 V ± 0.3 V 100
VCC = 5 V ± 0.5 V 20
2.1
0.9
CC
–4
V
V
V
m
A
m
A
4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
PARAMETER
MIN
MAX
UNIT
A or B
Y
C
15 pF
ns
A or B
Y
C
50 pF
ns
PARAMETER
MIN
MAX
UNIT
A or B
Y
C
15 pF
ns
A or B
Y
C
pF
ns
SN74AHC1G02
SINGLE 2-INPUT POSITIVE-NOR GATE
SCLS342F – APRIL 1996 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
MIN TYP MAX
V
V
m
A
m
A
V
V
I
I
C
OH
OL
I
CC
i
CC
2 V 1.9 2 1.9
IOH = –50 mA
IOH = –4 mA 3 V 2.58 2.48
IOH = –8 mA 4.5 V 3.94 3.8
IOL = 50 mA
IOL = 4 mA 3 V 0.36 0.44
IOL = 8 mA 4.5 V 0.36 0.44
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1
VI = VCC or GND, IO = 0 5.5 V 1 10
VI = VCC or GND 5 V 4 10 10 pF
3 V 2.9 3 2.9
4.5 V 4.4 4.5 4.4
2 V 0.1 0.1
3 V 0.1 0.1
4.5 V 0.1 0.1
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C
MIN TYP MAX
5.6 7.9 1 9.5
5.6 7.9 1 9.5
8.1 11.4 1 13
8.1 11.4 1 13
t
PLH
t
PHL
t
PLH
t
PHL
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
p
=
L
p
=
L
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PLH
t
PHL
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 15 pF
pd
p
=
L
p
= 50
L
= 5 V, T
CC
PARAMETER TEST CONDITIONS TYP UNIT
= 25°C
A
TA = 25°C
MIN TYP MAX
3.6 5.5 1 6.5
3.6 5.5 1 6.5
5.1 7.5 1 8.5
5.1 7.5 1 8.5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74AHC1G02
SINGLE 2-INPUT POSITIVE-NOR GATE
SCLS342F – APRIL 1996 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
C
(see Note A)
V
RL = 1 kΩ
L
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
w
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
50% V
50% V
VOLTAGE WAVEFORMS
50% V
CC
CC
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
CC
0 V
t
PHL
V
t
PLH
CC
V
V
CC
V
OH
OL
OH
OL
50% V
50% V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
50% V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
50% V
50% V
CC
CC
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CC
t
50% V
50% V
h
CC
CC
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈V
V
OL
V
OH
≈0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
Loading...