Datasheet SN74AHC174D, SN74AHC174DBR, SN74AHC174DGVR, SN74AHC174DR, SN74AHC174N Datasheet (Texas Instruments)
...
SN54AHC174, SN74AHC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS425E – JUNE 1998 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Operating Range 2-V to 5.5-V V
D
Contain Six Flip-Flops With Single-Rail
CC
Outputs
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
SN54AHC174 ...J OR W PACKAGE
SN74AHC174 . . . D, DB, DGV, N, OR PW PACKAGE
SN54AHC174 . . . FK PACKAGE
CLR
1Q
1D
2D
2Q
3D
3Q
GND
(TOP VIEW)
16
1
15
2
14
3
13
4
12
5
11
6
10
7
8
(TOP VIEW)
V
CC
6Q
6D
5D
5Q
4D
4Q
CLK
9
– 1000-V Charged-Device Model (C101)
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
1D
2D
NC
2Q
3D
1Q
3212019
4
5
6
7
8
910111213
CLR
NC
V
CC
6Q
18
17
16
15
14
6D
5D
NC
5Q
4D
description
NC
CLK
4Q
3Q
The ’AHC174 devices are positive-edge-triggered
D-type flip-flops with a direct clear (CLR) input and
are designed for 2-V to 5.5-V V
operation.
CC
NC – No internal connection
GND
Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low
level, the D input has no effect at the output.
The SN54AHC174 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AHC174 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
INPUTS
CLR CLK D
L X X L
H ↑ HH
H ↑ LL
H L X Q
OUTPUT
Q
0
Copyright 2000, Texas Instruments Incorporated
1
SN54AHC174, SN74AHC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS425E – JUNE 1998 – REVISED JANUARY 2000
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
†
1
CLR
9
CLK C1
3
1D
4
2D
6
3D
11
4D
13
5D
14
6D
R
1D
logic diagram (positive logic)
1
CLR
9
CLK
1D
3
1D
C1
R
10
12
15
2
1Q
5
2Q
7
3Q
4Q
5Q
6Q
2
1Q
To Five Other Channels
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
mA
mA
Dt/DvInput transition rise or fall rate
ns/V
SN54AHC174, SN74AHC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS425E – JUNE 1998 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AHC174 SN74AHC174
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 3 V
VCC = 5.5 V 3.85 3.85
VCC = 2 V 0.5 0.5
VCC = 3 V
VCC = 5.5 V 1.65 1.65
VCC = 2 V –50 –50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V –8 –8
VCC = 2 V 50 50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 8 8
VCC = 3.3 V ± 0.3 V 100 100
VCC = 5 V ± 0.5 V 20 20
2.1 2.1
0.9 0.9
CC
–4 –4
4 4
0 V
CC
V
V
V
m
A
m
A
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54AHC174, SN74AHC174
PARAMETER
TEST CONDITIONS
V
UNIT
OH
OL
UNIT
twPulse duration
ns
tsuSetup time before CLK↑
ns
UNIT
twPulse duration
ns
tsuSetup time before CLK↑
ns
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS425E – JUNE 1998 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
2 V 1.9 2 1.9 1.9
IOH = –50 mA
V
OH
IOH = –4 mA
IOH = –8 mA
IOL = 50 mA
V
OL
IOL = 4 mA
IOL = 8 mA
I
I
I
CC
C
i
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
VI = VCC or GND 0 V to 5.5 V ± 0.1 ± 1* ± 1
VI = VCC or GND, IO = 0 5.5 V 4 40 40
VI = VCC or GND 5 V 1.7 10 10 pF
3 V 2.9 3 2.9 2.9
4.5 V 4.4 4.5 4.4 4.4
3 V 2.58 2.48 2.48
4.5 V 3.94 3.8 3.8
2 V 0.1 0.1 0.1
3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
3 V 0.36 0.5 0.44
4.5 V 0.36 0.5 0.44
TA = 25°C SN54AHC174 SN74AHC174
MIN TYP MAX MIN MAX MIN MAX
V
V
m
A
m
A
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted)
TA = 25°C SN54AHC174 SN74AHC174
MIN MAX MIN MAX MIN MAX
CLR low 5 5 5
CLK high or low 5 5 5
p
t
Hold time, data after CLK↑ 0 0 0 ns
h
Data 5 6 6
CLR inactive 3 3 3
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted)
TA = 25°C SN54AHC174 SN74AHC174
MIN MAX MIN MAX MIN MAX
CLR low 5 5 5
CLK high or low 5 5 5
p
t
Hold time, data after CLK↑ 0.5 0.5 0.5 ns
h
Data 4.5 4.5 4.5
CLR inactive 2.5 2.5 2.5
= 3.3 V± 0.3 V
CC
= 5 V ± 0.5 V
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
UNIT
f
MH
CLK
Any Q
C
pF
ns
CLK
Any Q
C
pF
ns
PARAMETER
UNIT
f
MH
CLK
Any Q
C
15 pF
ns
CLK
Any Q
C
50 pF
ns
SN54AHC174, SN74AHC174
HEX D-TYPE FLIP-FLOPS
SCLS425E – JUNE 1998 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PHL
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
CLR Any Q CL = 15 pF 4.5* 11.4* 1* 13.5* 1 13.5 ns
CLR Any Q CL = 50 pF 6 14.9 1 17 1 17 ns
CL = 15 pF 95* 170* 80* 80
CL = 50 pF 55 130 50 50
p
= 15
L
p
= 50
L
CL = 50 pF 1.5** 1.5 ns
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PHL
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
CLR Any Q CL = 15 pF 3* 7.6* 1* 9* 1 9 ns
CLR Any Q CL = 50 pF 4.2 9.6 1 11 1 11 ns
CL = 15 pF 130* 240* 110* 110
CL = 50 pF 90 180 80 80
p
=
L
p
=
L
CL = 50 pF 1** 1 ns
TA = 25°C SN54AHC174 SN74AHC174
MIN TYP MAX MIN MAX MIN MAX
5.8* 11* 1* 13* 1 13
5.8* 11* 1* 13* 1 13
7.5 14.5 1 16.5 1 16.5
7.5 14.5 1 16.5 1 16.5
TA = 25°C SN54AHC174 SN74AHC174
MIN TYP MAX MIN MAX MIN MAX
4.1* 7.2* 1* 8.5* 1 8.5
4.1* 7.2* 1* 8.5* 1 8.5
5.5 9.2 1 10.5 1 10.5
5.5 9.2 1 10.5 1 10.5
WITH CLEAR
z
z
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance No load, f = 1 MHz 15.2 pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54AHC174, SN74AHC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS425E – JUNE 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
V
RL = 1 kΩ
C
L
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
VOLTAGE WAVEFORMS
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
w
50% V
CC
PULSE DURATION
50% V
CC
50% V
50% V
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
50% V
CC
CC
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
CC
t
PHL
50% V
t
PLH
50% V
0 V
V
CC
V
V
CC
V
OH
OL
OH
OL
Timing Input
(see Note B)
(see Note B)
Data Input
Output
Control
Output
Waveform 1
S1 at V
CC
Output
Waveform 2
S1 at GND
50% V
CC
t
CC
CC
h
50% V
50% V
CC
CC
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈V
V
OL
V
OH
≈0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 2000, Texas Instruments Incorporated
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