Texas Instruments SN74AHC16541DGVR, SN74AHC16541DL, SN74AHC16541DLR Datasheet

SN54AHC16541, SN74AHC16541

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCLS332F – MARCH 1996 – REVISED JANUARY 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Operating Range 2-V to 5.5-V V

CC

D

Distributed VCC and GND Pins Minimize
High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description

The ’AHC16541 devices are noninverting 16-bit
buffers composed of two 8-bit sections with
separate output-enable signals. For either 8-bit
buffer section, the two output-enable (1OE1 and
1OE2

or 2OE1 and 2OE2) inputs must be low for
the corresponding Y outputs to be active. If either
output-enable input is high, the outputs of that
8-bit buffer section are in the high-impedance
state.

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54AHC16541 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHC16541 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 8-bit buffer/driver)

INPUTS

OUTPUT

OE1

OE2 A

Y

L L L L
L LH H
H XX Z
X H X Z

Copyright  2000, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

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19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1OE1

1Y1
1Y2

GND

1Y3
1Y4

V

CC

1Y5
1Y6

GND

1Y7
1Y8
2Y1
2Y2

GND

2Y3
2Y4

V

CC

2Y5
2Y6

GND

2Y7
2Y8

2OE1

1OE2
1A1
1A2
GND
1A3
1A4
V

CC

1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V

CC

2A5
2A6
GND
2A7
2A8
2OE2

SN54AHC16541 . . . WD PACKAGE

SN74AHC16541 . . . DGG, DGV, OR DL PACKAGE

(TOP VIEW)

SN54AHC16541, SN74AHC16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCLS332F – MARCH 1996 – REVISED JANUARY 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

25

47

1A1 1Y1

2

46

1A2

1Y2

3

44

1A3 1Y3

5

43

1A4 1Y4

6

41

1A5 1Y5

8

40

1A6 1Y6

9

38

1A7 1Y7

11

37

1A8 1Y8

12

36

2A1 2Y1

13

35

2A2

2Y2

14

33

2A3 2Y3

16

32

2A4 2Y4

17

30

2A5 2Y5

19

29

2A6 2Y6

20

27

2A7

2Y7

22

26

2A8 2Y8

23

24

48

1

1OE1
1OE2
2OE1

2OE2

&

&

EN1

EN2

111

2

logic diagram (positive logic)

1OE1
1OE2

2OE1
2OE2

1A1 1Y1

2Y1

2A1

To Seven Other Channels To Seven Other Channels

1
48

47

24
25

36

2

13

SN54AHC16541, SN74AHC16541

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCLS332F – MARCH 1996 – REVISED JANUARY 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

(see Note 1) –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

O

(V

O

= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 3)

SN54AHC16541 SN74AHC16541

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 2 5.5 2 5.5 V

VCC = 2 V 1.5 1.5

V

IH

High-level input voltage

VCC = 3 V

2.1 2.1

V
VCC = 5.5 V 3.85 3.85
VCC = 2 V 0.5 0.5

V

IL

Low-level input voltage

VCC = 3 V

0.9 0.9

V
VCC = 5.5 V 1.65 1.65

V

I

Input voltage 0 5.5 0 5.5 V

V

O

Output voltage 0 V

CC

0 V

CC

V
VCC = 2 V –50 –50

m

A

I

OH

High-level output current

VCC = 3.3 V ± 0.3 V

–4 –4

VCC = 5 V ± 0.5 V –8 –8

mA

VCC = 2 V 50 50

m

A

I

OL

Low-level output current

VCC = 3.3 V ± 0.3 V

4 4

VCC = 5 V ± 0.5 V 8 8

mA

p

VCC = 3.3 V ± 0.3 V 100 100

∆t/∆vInput transition rise or fall rate

VCC = 5 V ± 0.5 V 20 20

ns/V

T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

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