Texas Instruments SN74AHC16540DGGR, SN74AHC16540DGVR, SN74AHC16540DL, SN74AHC16540DLR Datasheet
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Operating Range 2-V to 5.5-V V
CC
D
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 16-bit buffers and bus drivers provide a
high-performance bus interface for wide data
paths.
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1
or OE2) input is high, all corresponding
outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHC16540 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHC16540 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit buffer/driver)
INPUTS
OUTPUT
OE1 OE2
A
Y
L L L H
L LH L
H XX Z
X H X Z
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
SN54AHC16540 . . . WD PACKAGE
SN74AHC16540 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
V
CC
2Y5
2Y6
GND
2Y7
2Y8
2OE1
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE2
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
47
1A1
1
1Y1
2
48
46
1A2 1Y2
3
24
25
44
1A3 1Y3
5
43
1A4 1Y4
6
41
1A5 1Y5
8
40
1A6
1Y6
9
38
1A7 1Y7
11
37
1A8 1Y8
12
36
2A1 2Y1
13
35
2A2 2Y2
14
33
2A3 2Y3
16
32
2A4 2Y4
17
30
2A5
2Y5
19
29
2A6 2Y6
20
27
2A7 2Y7
22
26
2A8 2Y8
23
1OE1
1OE2
2OE1
2OE2
&
&
11
12
EN1
EN2
logic diagram (positive logic)
1OE1
1OE2
2OE1
2OE2
1A1 1Y1
2Y1
2A1
To Seven Other Channels To Seven Other Channels
1
48
47
24
25
36
2
13
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54AHC16540 SN74AHC16540
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage
VCC = 3 V
2.1 2.1
V
VCC = 5.5 V 3.85 3.85
VCC = 2 V 0.5 0.5
V
IL
Low-level input voltage
VCC = 3 V
0.9 0.9
V
VCC = 5.5 V 1.65 1.65
V
I
Input voltage 0 5.5 0 5.5 V
V
O
Output voltage 0 V
CC
0 V
CC
V
VCC = 2 V –50 –50
m
A
I
OH
High-level output current
VCC = 3.3 V ± 0.3 V
–4 –4
VCC = 5 V ± 0.5 V –8 –8
mA
VCC = 2 V 50 50
m
A
I
OL
Low-level output current
VCC = 3.3 V ± 0.3 V
4 4
VCC = 5 V ± 0.5 V 8 8
mA
p
VCC = 3.3 V ± 0.3 V 100 100
∆t/∆vInput transition rise or fall rate
VCC = 5 V ± 0.5 V 20 20
ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54AHC16540 SN74AHC16540
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 2 1.9 1.9
IOH = –50 mA
3 V 2.9 3 2.9 2.9
V
OH
4.5 V 4.4 4.5 4.4 4.4
V
IOH = –4 mA 3 V 2.58 2.48 2.48
IOH = –8 mA 4.5 V 3.94 3.8 3.8
2 V 0.1 0.1 0.1
IOL = 50 mA
3 V 0.1 0.1 0.1
V
OL
4.5 V 0.1 0.1 0.1
V
IOL = 4 mA 3 V 0.36 0.5 0.44
IOL = 8 mA 4.5 V 0.36 0.5 0.44
I
I
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
m
A
I
OZ
VO = VCC or GND,
VI (OE
) = VIL or V
IH
5.5 V ±0.25 ±2.5 ±2.5
m
A
I
CC
VI = VCC or GND, IO = 0 5.5 V 4 40 40
m
A
C
i
VI = VCC or GND 5 V 2 10 10 pF
C
o
VO = VCC or GND 5 V 3 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
FROM TO LOAD
TA = 25°C SN54AHC16540 SN74AHC16540
PARAMETER
(INPUT) (OUTPUT) CAPACITANCE
MIN TYP MAX MIN MAX MIN MAX
UNIT
t
PLH
p
4.8** 8.4** 1** 10** 1 10
t
PHL
AYC
L
= 15
pF
4.8** 8.4** 1** 10** 1 10
ns
t
PZH
p
6.8** 10.6** 1** 12.5** 1 12.5
t
PZL
OE
Y
C
L
= 15
pF
6.8** 10.6** 1** 12.5** 1 12.5
ns
t
PHZ
p
6.8** 11.5** 1** 12.5** 1 12.5
t
PLZ
OE
Y
C
L
= 15
pF
6.8** 11.5** 1** 12.5** 1 12.5
ns
t
PLH
p
7.7 11 1 12.5 1 12.5
t
PHL
AYC
L
= 50
pF
7.3 11 1 12.5 1 12.5
ns
t
PZH
p
9.7 14.1 1 16 1 16
t
PZL
OE
Y
C
L
= 50
pF
7.1 14.1 1 16 1 16
ns
t
PHZ
p
9.4 14 1 16 1 16
t
PLZ
OE
Y
C
L
=
50 pF
9.7 14 1 16 1 16
ns
t
sk(o)
CL = 50 pF 1.5*** 1.5 ns
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM TO LOAD
TA = 25°C SN54AHC16540 SN74AHC16540
PARAMETER
(INPUT) (OUTPUT) CAPACITANCE
MIN TYP MAX MIN MAX MIN MAX
UNIT
t
PLH
p
3.7* 6* 1* 7* 1 7
t
PHL
AYC
L
=
15 pF
3.7* 6* 1* 7* 1 7
ns
t
PZH
p
4.7* 7.3* 1* 8.5* 1 8.5
t
PZL
OE
Y
C
L
=
15 pF
4.7* 7.3* 1* 8.5* 1 8.5
ns
t
PHZ
p
4.5* 7.2* 1* 8.5* 1 8.5
t
PLZ
OE
Y
C
L
= 15
pF
4.5* 7.2* 1* 8.5* 1 8.5
ns
t
PLH
p
5.2 8 1 9 1 8.5
t
PHL
AYC
L
=
50 pF
5.2 8 1 9 1 8.5
ns
t
PZH
p
6.2 9.3 1 10.5 1 10.5
t
PZL
OE
Y
C
L
=
50 pF
6.2 9.3 1 10.5 1 10.5
ns
t
PHZ
p
6 9.2 1 10.5 1 10.5
t
PLZ
OE
Y
C
L
= 50
pF
6 9.2 1 10.5 1 10.5
ns
t
sk(o)
CL = 50 pF 1
**
1 ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, TA = 25°C (see Note 4)
SN74AHC16540
PARAMETER
MIN TYP MAX
UNIT
V
OL(P)
Quiet output, maximum dynamic V
OL
0.6 V
V
OL(V)
Quiet output, minimum dynamic V
OL
–0.3 V
V
OH(V)
Quiet output, minimum dynamic V
OH
4.7 V
V
IH(D)
High-level dynamic input voltage 3.5 V
V
IL(D)
Low-level dynamic input voltage 1.5 V
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance No load, f = 1 MHz 13 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% V
CC
V
CC
V
CC
0 V
0 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
V
CC
0 V
50% V
CC
50% V
CC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
≈V
CC
0 V
50% V
CC
VOL + 0.3 V
50% V
CC
≈0 V
V
CC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
TEST S1
V
CC
0 V
50% V
CC
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
V
CC
RL = 1 kΩ
GND
From Output
Under Test
C
L
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% V
CC
50% V
CC
50% V
CC
50% V
CC
50% V
CC
50% V
CC
50% V
CC
50% V
CC
VOH – 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 2000, Texas Instruments Incorporated
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