Texas Instruments SN74ACT8997DW, SN74ACT8997DWR, SN74ACT8997NT, SNJ54ACT8997FK, SNJ54ACT8997JT Datasheet

SN54ACT8997, SN74ACT8997

SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES

SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

D

Members of the Texas Instruments

SCOPE

D

Compatible With the IEEE Standard

 Family of Testability Products

1149.1-1990 (JTAG) Serial Test Bus

D

Allow Partitioning of System Scan Paths

D

Can Be Cascaded Horizontally or Vertically

D

Select Up to Four Secondary Scan Paths to
Be Included in a Primary Scan Path

D

Include 8-Bit Programmable Binary Counter
to Count or Initiate Interrupt Signals

D

Include 4-Bit Identification Bus for
Scan-Path Identification

D

Inputs Are TTL Compatible

D

EPIC

 (Enhanced-Performance Implanted

CMOS) 1-µm Process

D

Package Options Include Plastic

SN54ACT8997 ...JT PACKAGE

SN74ACT8997 . . . DW OR NT PACKAGE

DTDO1
DTDO2
DTDO3
DTDO4

DTMS1
DTMS2
DTMS3
DTMS4

DTCK

DCO

MCO

GND

TDO
TMS

(TOP VIEW)

1

28

2

27

3

26

4

25

5

24

6

23

7

22

8

21

9

20

10

19

11

18

12

17

13

16

14

15

DCI
MCI
TRST
ID1
ID2
ID3
ID4
V

CC

DTDI1
DTDI2
DTDI3
DTDI4
TDI
TCK

Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs

description

The ’ACT8997 are members of the Texas
Instruments SCOPE testability integrated-
circuit family . This family of components facilitates
testing of complex circuit-board assemblies.

The ’ACT8997 enhance the scan capability of TI’s
SCOPE family by allowing augmentation of a
system’s primary scan path with secondary scan
paths (SSPs), which can be individually selected
by the ’ACT8997 for inclusion in the primary scan

SN54ACT8997 . . . FK PACKAGE

TRST

MCI

DCI

DCO

MCO
DTDO1
DTDO2

5
6
7
8
9
10
11

ID1

4

12

(TOP VIEW)

ID2

ID3

321

15 16 17 18

13 14

CC

ID4

V

28 27 26

DTDI1

DTDI2

25
24
23
22
21
20
19

path. These devices also provide buffering of test
signals to reduce the need for external logic.

By loading the proper values into the instruction

DTDO4

DTDO3

GND

DTMS1

DTMS2

DTMS3

DTMS4

register and data registers, the user can select up
to four SSPs to be included in a primary scan path. Any combination of the SSPs can be selected at a time. Any
of the device’s six data registers or the instruction register can be placed in the device’s scan path, i.e., placed
between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations.

DTDI3
DTDI4
TDI
TCK
TMS
TDO
DTCK

All operations of the device except counting are synchronous to the test clock pin (TCK). The 8-bit
programmable up/down counter can be used to count transitions on the device condition input (DCI) pin and
output interrupt signals via the device condition output (DCO) pin. The device can be configured to count on
either the rising or falling edge of DCI.

The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.
The SN54ACT8997 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ACT8997 is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1996, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

functional block diagram

3

DTDO1

TDI

DTDI1

DTDI2

DTDI3

DTDI4

DCI

MCI

ID(1–4)

V

CC

16

V

CC

20

V

CC

19

V

CC

18

V

CC

17

28

27

22–25

Scan-Path

Configuration

Data

Registers

Instruction

Register

4

DTDO2

5

DTDO3

6

DTDO4

2

MCO

1

DCO
(3 state or
open drain)

8

DTMS1

9

DTMS2

10

DTMS3

11

DTMS4

13

TDO

V

CC

14

TMS

15

TCK

V

CC

26

TRST

Pin numbers shown are for the DW, JT, and NT packages.

2

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Test Port

12

DTCK

SN54ACT8997, SN74ACT8997

SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES

SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

functional block description

The ’ACT8997 is intended to link secondary scan paths for inclusion in a primary scan path. Any combination
of the four secondary scan paths can be linked, or the device can be bypassed entirely.

The least-significant bit (LSB) of any value scanned into any register of the device is the first bit shifted in
(nearest to TDO). The most-significant bit (MSB) is the last bit shifted in (nearest to TDI).

The ’ACT8997 is divided into functional blocks as detailed below.

test port

The test port decodes the signals on TCK, TMS, and TRST to control the operation of the circuit. The test port
includes a TAP controller that issues the proper control instructions to the data registers according to the
IEEE Standard 1149.1 protocol. The T AP controller state diagram is shown in Figure 1.

instruction register

The instruction register (IR) is an 8-bit-wide serial-shift register that issues commands to the device. Data is
input to the instruction register via TDI (or one of the DTDI pins) and shifted out via TDO. All device operations
are initiated by loading the proper instruction or sequence of instructions into the IR.

data registers

Six parallel data registers are included in the ’ACT8997: bypass, control, counter, boundary-scan, ID-bus, and
select. The ID bus register is a part of the boundary-scan register. Each data register is serially loaded via TDI
or DTDI and outputs data via TDO. Table 1 summarizes the registers in the ’ACT8997.

scan-path-configuration circuit

This circuit decodes bits in the select and control registers to determine which, if any, of the secondary scan
paths are to be included in the primary scan path.

T able 1. Register Summary

REGISTER

NAME

Instruction 8 Issue command information to the device
Control 10 Configuration and enable control
Counter 8 Count events on DCI, output interrupts via DCO
Select 8 Select one or more secondary scan paths
Boundary Scan 10 Capture and force test data at device periphery
ID Bus 4 Provide subsystem identification code
Bypass 1 Remove the ’ACT8997 from the scan path

LENGTH

(BITS)

FUNCTION

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

Terminal Functions

TERMINAL

NAME

DCI I

DCO O

DTCK O Device test clock. DTCK outputs the buffered test clock TCK to the secondary scan path(s).

DTDI1
DTDI2
DTDI3
DTDI4

DTDO1
DTDO2
DTDO3
DTDO4

DTMS1
DTMS2
DTMS3
DTMS4

GND Ground

IDI
ID2
ID3
ID4

MCI I

MCO O Master condition output. MCO transmits interrupt and protocol signals to the secondary scan path(s).

TCK I

TDI I

TDO O

TMS I

TRST

V

CC

I/O DESCRIPTION

Device condition input. DCI receives interrupt and protocol signals from the secondary scan path(s). When the
counter register is instructed to count up or down, DCI is configured as the counter clock.

Device condition output. DCO is configured by the control register to output protocol and interrupt signals and can
be configured by the control register to output an error signal if the instruction register is loaded with an invalid value.
DCO is further configured by the control register as:

Active high or active low (reset condition = active low)
Open drain or 3 state (reset condition = open drain)

Device test data input 1–4. DTDI1–DTDI4 receive the serial test data output(s) of the selected secondary scan

I

path(s). An internal pullup forces DTDI1–DTDI4 to a high logic level if it is left unconnected.

O Device test data output 1–4. These outputs send serial test data to the TDI input(s) of the secondary scan path(s).

Device test mode select 1–4. Any combination of these four outputs can be selected to follow TMS to direct the
secondary scan path(s) through the TAP controller states in Figure 1. The unselected DTMS outputs can be set

O

independently to a high or low logic level. The TMS circuit monitors input from the select register to determine the
configuration of the DTMS outputs.

Identification 1–4. This 4-bit data bus can be hardwired to provide identification of the subsystem under test. The

I

value present on the bus can be scanned out through the boundary scan or ID bus registers.

Master condition input. MCI receives interrupt and protocol signals from a primary bus controller (PBC). The level
on MCI is buffered and output on MCO.

Test clock. One of four terminals required by IEEE Standard 1149.1. All operations of the ’ACT8997 except for the
count function are synchronous to TCK. Data on the device inputs is captured on the rising edge of TCK, and outputs
change on the falling edge of TCK.

T est data input. One of four terminals required by IEEE Standard 1149.1. TDI is the serial input for shifting information
into the instruction register or selected data register . TDI is typically driven by the TDO of the PBC. An internal pullup
forces TDI to a high level if left unconnected.

Test data output. One of four terminals required by IEEE Standard 1149.1. TDO is the serial output for shifting
information out of the instruction register or selected data register . TDO is typically connected to the TDI of the next
scannable device in the primary scan path.

Test mode select. One of four terminals required by IEEE Standard 1149.1. The level of TMS at the rising edge of
TCK directs the ’ACT8997 through its TAP controller states. An internal pullup forces TMS to a high level if left
unconnected.

Test reset. This active-low input implements the optional reset terminal of IEEE Standard 1149.1. When asserted,
TRST

I

causes the ’ACT8997 to go to the Test-Logic-Reset state and configure the instruction register and data

registers to their power-up values. An internal pullup forces TRST
Supply voltage

to a high level if left unconnected.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT8997, SN74ACT8997

SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES

SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

state diagram description

The T AP proceeds through the states in Figure 1 according to IEEE Standard 1149.1. There are six stable states
(indicated by a looping arrow) and ten unstable states in the diagram. A stable state is a state the T AP can retain
for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to manipulate a data register and one to manipulate
the instruction register. No more than one register can be manipulated at a time.

Test-Logic-Reset

TMS = H

TMS = L

TMS = L

Run-Test/Idle

TMS = H

TMS = H

Select-DR-Scan Select-IR-Scan

TMS = L

Capture-DR

TMS = L

Shift-DR

TMS = L TMS = L

TMS = H TMS = H

TMS = H

Exit1-DR

TMS = L TMS = L

Pause-DR

TMS = L

TMS = H

TMS = H

TMS = L

TMS = H TMS = H

Capture-IR

TMS = L

Shift-IR

Exit1-IR

Pause-IR

TMS = H

TMS = L TMS = L

TMS = H

TMS = L

Exit2-DR

TMS = H

Update-DR

TMS = H TMS = H

TMS = L TMS = L

Figure 1. TAP-Controller State Diagram

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Exit2-IR

TMS = H

Update-IR

5

SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

Test-Logic-Reset

In this state, the test logic is inactive and an internal reset signal is applied to all registers in the device. During
device operation, the TAP returns to this state in no more than five TCK cycles if the test mode select (TMS)
input is high. The TMS pin has an internal pullup that forces it to a high level if it is left unconnected or if a board
defect causes it to be open circuited. The device powers up in the Test-Logic-Reset state.

Run-Test/Idle

The TAP must pass through this state before executing any test operations. The TAP may retain this state
indefinitely , and no registers are modified while in Run-T est/Idle. The 8-bit programmable up/down counter can
be operated in this state.

Select-DR-Scan, Select-IR-Scan

No specific function is performed in these states; the TAP exits either of them on the next TCK cycle.

Capture-DR

The selected data register is placed in the scan path (i.e., between TDI and TDO). Depending on the current
instruction, data may or may not be loaded or captured by that register on the rising edge of TCK, causing the
TAP state to change.

Shift-DR

In this state, data is serially shifted through the selected data register from TDI to TDO on each TCK cycle. The
first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK
cycle in which the T AP changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). On the falling edge
of TCK in Shift-DR, TDO goes from the high-impedance state to the active state. TDO enables to the value
present in the least-significant bit of the selected data register.

Exit1-DR, Exit2-DR

These are temporary states that end the shifting process. It is possible to return to the Shift-DR state from either
Exit1-DR or Exit2-DR without recapturing the data register. The last shift occurs on the TCK cycle in which the
T AP state changes from Shift-DR to Exit-DR. TDO changes from the active state to the high-impedance state
on the falling edge of TCK in Exit1-DR.

Pause-DR

The TAP can remain in this state indefinitely. The Pause-DR state suspends and resumes shift operations
without loss of data.

Update-DR

If the current instruction calls for the latches in the selected data register to be updated with current data, the
latches are updated only during this state.

Capture-IR

The instruction register is preloaded with the IR status word (see Table 4) and placed in the scan path.

Shift-IR

In this state, data is serially shifted through the instruction register from TDI to TDO on each TCK cycle. The
first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK
cycle in which the T AP changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). On the falling edge of
TCK in Shift-IR, TDO goes from the high-impedance state to the active state, and will enable to a high level.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT8997, SN74ACT8997

SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES

SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

Exit1-IR, Exit2-IR

These are temporary states that end the shifting process. It is possible to return to the Shift-IR state from either
Exit1-IR or Exit2-IR without recapturing the instruction register. The last shift occurs on the TCK cycle in which
the T AP state changes from Shift-IR to Exit1-IR. TDO changes from the active state to the high-impedance state
on the falling edge of TCK in Exit1-IR.

Pause-IR

The T AP can remain in this state indefinitely. The Pause-IR state suspends and resumes shift operations without
loss of data.

Update-IR

In this state, the latches shadowing the instruction register are updated with the new instruction.

instruction-register description

The instruction register (IR) is an 8-bit serial register that outputs control signals to the device. Table 2 lists the
instructions implemented in the ’ACT8997 and the data register selected by each instruction. The MSB of the
IR is an even-parity bit. If the value scanned into the IR during Shift-IR does not contain even parity, an error
signal (IRERR
via DCO if the TAP enters the Pause-IR state.

) is generated internally as shown in T able 3. The ’ACT8997 can be configured to output IRERR

During the Capture-IR state, the IR status word is loaded.The IR status word contains information about the
most recently loaded value of the instruction register and the logic level present at the DCI input. The IR status
word is encoded as shown in Table 4. Figure 2 shows the order of scan for the IR.

TDI or DTDI

Bit 7

(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

(LSB)

Figure 2. Instruction-Register Bits and Order of Scan

TDO

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7

SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

Table 2. Instruction-Register Opcodes

BINARY CODE

BIT 7 → BIT 0

MSB → LSB

00000000 00 EXTEST Boundary scan Boundary scan Test
10000001 81 BYPASS
10000010 82 SAMPLE/PRELOAD Sample boundary Boundary scan Normal
0000001 1 03 INTEST Boundary scan Boundary scan Test
10000100 84 BYPASS
00000101 05 BYPASS
00000110 06 BYPASS
10000111 87 BYPASS
10001000 88 COUNT Count Bypass Normal
00001001 09 COUNT Count Bypass Normal
00001010 0A BYPASS
10001011 8B BYPASS
00001100 0C BYPASS
10001101 8D BYPASS Bypass scan Bypass Normal
10001110 8E SCANCN Control register scan Control Normal

00001 111 0F SCANCN Control register scan Control Normal
11111010 FA SCANCNT Counter scan Counter Normal
01111011 7B READCNT Counter read Counter Normal
11111100 FC SCANIDB ID bus register scan ID bus Normal
01111101 7D READIDB ID bus register read ID bus Normal
01111110 7E SCANSEL Select register scan Select Normal
All others BYPASS Bypass scan Bypass Normal

†

A SCOPE opcode exists but is not supported by the ’ACT8997.

HEX

VALUE

SCOPE OPCODE DESCRIPTION

SELECTED DATA

REGISTER

†

†
†
†
†

†
†
†

Bypass scan Bypass Normal

Bypass scan Bypass Normal
Bypass scan Bypass Normal
Bypass scan Bypass Normal
Bypass scan Bypass Normal

Bypass scan Bypass Normal
Bypass scan Bypass Normal
Bypass scan Bypass Normal

MODE

Table 3. IRERR Function Table

NO. OF INSTRUCTION

REGISTER BITS = 1

0, 2, 4, 6, 8 1

1, 3, 5, 7 0

IRERR

Table 4. Instruction-Register Status Word

IR BIT VALUE

7 IRERR (see Table 3)
6 0
5 0
4 0
3 DCI (1 = active, 0 = inactive)
2 0
1 0
0 1

†

This value is loaded in the instruction
register during the Capture-IR TAP state.

†

8

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