Texas Instruments SN74ACT8994FN Datasheet

IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER

D

Member of the Texas Instruments
Family of Testability Products

D

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture

D

Contains a 1024-Word by 16-Bit
Random-Access Memory (RAM) to Store
the States of a Digital Bus

D

Test Operations Are Synchronous to the
Test Clock or System Clock(s)

D

Contains T exas Instruments Event
Qualification Module for Real-Time System
Test

D

Eight Protocols for On-Line Signal
Monitoring and Test Operations

D

Inputs Are TTL-Voltage Compatible

SCOPE



D

D

D

D

D

D

D

FN PACKAGE

(TOP VIEW)

SN74ACT8994

DIGITAL BUS MONITOR

SCAS196E – JULY 1990 – REVISED DECEMBER 1996

Performs Parallel-Signature Analysis (PSA)
of Data Inputs With User-Definable
Feedback

Data Inputs Are Maskable During PSA
Operations

Cascaded PSA Mode Allows Compression
of Parallel Data Paths Greater Than 16 Bits
in Width

Direct Memory Access (DMA) Speeds
Memory and Register File Read/Write
Operations

Power-Down Mode When RAM Is Idling
Reduces Power Dissipation

EPIC

 (Enhanced-Performance Implanted

CMOS) 1-µm Process
Packaged in 28-Pin Plastic Chip Carriers

GND

EQO

CC

PIO

EQI

25
24
23
22
21
20
19

D15

D8
D9
D10
D11
D12
D13
D14

D1

D0
CLK1
CLK2
CLK3

TMS

TCK

D2D3D4D5VD6D7

3212827

426

5
6
7
8
9
10
11

12 13 14 15 16 1718

TDI

TDO

description

The SN74ACT8994 digital bus monitor (DBM) is a member of the Texas Instruments SCOPE testability
integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary
scan to facilitate testing of complex circuit-board assemblies. The DBM is a boundary-scannable device
designed to monitor and/or store the values of a digital bus up to 16 bits in width. It resides in parallel with the
bus being monitored.

Data at the D-input pins can be stored in a scannable random-access memory (RAM). Up to 1024 words of
16 bits can be stored. A parallel-signature analysis (PSA) can be performed on the data or on the contents of
memory . The PSA operations use a linear-feedback shift-register technique to compress data into a signature.
The user can configure the device to mask any combination of data inputs and control the feedback used during
PSA operations.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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Copyright  1996, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

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SN74ACT8994
DIGITAL BUS MONITOR
IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER

SCAS196E – JULY 1990 – REVISED DECEMBER 1996

description (continued)

The DBM receives instructions via the IEEE Standard 1 149.1-1990 test access port (TAP) interface. The TAP
interface consists of test clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO)
pins.

The DBM can be operated in the off-line mode or the on-line mode. In the off-line mode, the device performs
test operations independent of system conditions. Off-line test operations include parallel-signature analysis
(PSA) on the contents of RAM and external test.

In the on-line mode, the DBM can be configured to perform test operations that are initiated based on system
conditions and that operate synchronously to a logical combination of one or more system clocks. The device
allows sample, storage, and/or PSA operations to be performed according to one of eight protocols. Compare
patterns, which can be stored in the event-qualification module (EQM), allow the user to define specific values
of the 16-bit bus for which the test operations are to be performed.

The 1024-word by 16-bit RAM and the EQM register files can be serially accessed using
IEEE-Standard-1149.1-1990-compatible read and write instructions. However, direct memory access (DMA)
instructions also are provided to speed transfer of large amounts of data to and from the RAM and EQM.

The polynomial input/output (PIO) is a bidirectional pin used to cascade more than one DBM to provide
signature analysis on a bus larger than 16 bits.

The SN74ACT8994 is characterized for operation from 0°C to 70°C.

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IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER

functional block diagram

17

EQI

7

CLK1

8

CLK2

9

CLK3

6

D0

5

D1

4

D2

3

D3

2

D4

1

D5

Boundary-Scan Register

PCI

Test-Cell Register

16

RAM

SN74ACT8994

DIGITAL BUS MONITOR

SCAS196E – JULY 1990 – REVISED DECEMBER 1996

15

EQO

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

TDI

TMS

TCK

27

16

13

PIO

TDO

26

25

24

23

22

21

20

19

18

V

CC

12

V

CC

10

11

EQM

Control/
Bypass/

Header Registers

TDO
MUX

TAP Controller/

Instruction Register

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3

SN74ACT8994

I/O

DESCRIPTION

DIGITAL BUS MONITOR
IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER

SCAS196E – JULY 1990 – REVISED DECEMBER 1996

Terminal Functions

TERMINAL

NAME NO.

CLK1, CLK2, CLK3 7, 8, 9 I

D0, D1, D2, D3, D4,
D5, D6, D7, D8, D9,

D10, D11, D12,

D13, D14, D15

EQI 17 I

EQO 15 O

GND 14 Ground

PIO 16 I/O

TCK 11 I

TDI 12 I

TDO 13 O

TMS 10 I

V

CC

6, 5, 4, 3, 2,

1, 27, 26, 25

24, 23, 22,

21, 20, 19, 18

28 Supply voltage

Clock 1, 2, and 3. CLK1–CLK3 provide various types of system clock and control signals to the
DBM for the purpose of synchronizing test operations to the system under test.

Data bus inputs. D15–D0 form the 16-bit digital bus that is monitored by the DBM. Data that
appears at this bus can be compressed into a 16-bit signature and/or stored in the 1024-word

I

RAM. Each data bit can be individually masked during test operations.
Event-qualification input. EQI is used to receive an external (global) event signal from

user-defined event-qualification logic. EQI can be configured to initiate test operations in the
on-line mode.

Event-qualification output. EQO is used to transmit any of several internally generated status
signals. EQO can be configured to transmit internal (local) event signals to external (global)
event-qualification logic.

Polynominal input/output. PIO is used to cascade more than one DBM to provide signature
analysis on a bus larger than 16 bits. Its configuration as an input or output for a particular DBM
device depends on the significance (most, middle, or least) of that DBM in the scan path.

Test clock. One of four pins required by IEEE Standard 1149.1-1990. Scan operations of the
DBM are synchronous to TCK. Data is captured on the rising edge of TCK, and outputs change
on the falling edge of TCK.

T est data input. One of four pins required by IEEE Standard 1 149.1-1990. TDI is the serial input
for shifting data through the instruction register or selected data register. An internal pullup
forces TDI to a high level if left unconnected.

Test data output. One of four pins required by IEEE Standard 1149.1-1990. TDO is the serial
output for shifting data through the instruction register or selected data register.

Test mode select. One of four pins required by IEEE standard 1149.1-1990. TMS directs the
DBM through its TAP controller states. An internal pullup forces TMS to a high level if left
unconnected.

detailed description

The general architecture of the DBM is shown in the functional block diagram. The DBM contains eight data
registers and an instruction register that are accessed serially through the TAP. The TAP controller is a
finite-state machine that issues control and enable signals throughout the device, based on its current state.
The instruction register (IR) provides additional control signals that are specific to the current instruction. Test
data is transmitted serially from TDI through the scan path to TDO. The IR or one of the eight data registers is
always selected in the scan path by the TAP control signals issued to the TDO multiplexer.

The 1024-word RAM can be used to store data from the bus being monitored during test operations. The RAM
is accessed via the TAP interface when the RAM register (RAMR) is selected in the scan path.

The event-qualification module (EQM) contains two data registers that contain configuration, compare, and
mask data associated with on-line test operations. The EQM also contains the state machines for the eight
protocols that include various start/stop, start/pause/resume, and do-while algorithms. These protocols
operate synchronously to the clock signal generated by the programmable clock interface (PCI). The PCI
generates a clock signal from one of 32 different logical combinations of CLK1, CLK2, CLK3, and TCK. The user
configures the PCI through the control register (CTLR).

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