Texas Instruments SN74ACT86D, SN74ACT86DBLE, SN74ACT86DBR, SN74ACT86DR, SN74ACT86N Datasheet

SN54ACT86, SN74ACT86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCAS534A – AUGUST 1995 – REVISED APRIL 1996

D

Inputs Are TTL-Voltage Compatible

D

EPIC

 (Enhanced-Performance Implanted

CMOS) 1-µm Process

D

Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPS

description

The ’ACT86 are quadruple 2-input exclusive-OR
gates. The devices perform the Boolean functions
Y = A  B or Y = AB + AB in positive logic.

A common application is as a true/complement
element. If one of the inputs is low, the other input
is reproduced in true form at the output. If one of
the inputs is high, the signal on the other input is
reproduced inverted at the output.

The SN54ACT86 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ACT86 is characterized for
operation from –40°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

A B

L L L
L HH

H LH
H H L

OUTPUT

Y

SN54ACT86 ... J OR W PACKAGE

SN74ACT86 ... D, DB, N, OR PW PACKAGE

SN54ACT86 . . . FK PACKAGE

1Y

NC

2A

NC

2B

NC – No internal connection

(TOP VIEW)

1A
1B
1Y
2A
2B
2Y

GND

(TOP VIEW)

1B1ANC

3 2 1 20 19

4
5
6
7
8

910111213

2Y

1
2
3
4
5
6
7

GND

NC

14
13
12
11
10

9
8

V

3Y

CC

4B

18
17
16
15
14

3A

V
4B
4A
4Y
3B
3A
3Y

CC

4A
NC
4Y
NC
3B

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1996, Texas Instruments Incorporated

1

SN54ACT86, SN74ACT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCAS534A – AUGUST 1995 – REVISED APRIL 1996

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.

†

1A
1B
2A
2B

3A
3B

4A
4B

1
2
4
5

9
10

12
13

= 1

3

1Y

6

2Y

8

3Y

11

4Y

exclusive-OR logic

An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.

EXCLUSIVE-OR

= 1

These five equivalent exclusive-OR symbols are valid for an ’ACT86 gate in positive logic; negation may
be shown at any two ports.

LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT

= 2k 2k + 1

The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).

The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.

The output is active (high)
if an odd number of inputs
(i.e., only 1 of the 2) are
active.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT86, SN74ACT86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCAS534A – AUGUST 1995 – REVISED APRIL 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at TA = 55°C (in still air) (see Note 2):D package 1.25 W. . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

DB package 0.5 W. . . . . . . . . . . . . . . . . .

N package 1.1 W. . . . . . . . . . . . . . . . . . .

PW package 0.5 W. . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

MIN MAX MIN MAX UNIT

V

CC

V

IH

V

IL

V

I

V

O

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 8 0 8 ns/V
T

A

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
Output voltage 0 V
High-level output current –24 –24 mA
Low-level output current 24 24 mA

Operating free-air temperature –55 125 –40 85 °C

CC
CC

0 V
0 V

CC
CC

V
V

†

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3

SN54ACT86, SN74ACT86

PARAMETER

TEST CONDITIONS

V

UNIT

I

A

V

I

mA

V

I

A

V

I

mA

V

PARAMETER

UNIT

A or B

Y

ns

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCAS534A – AUGUST 1995 – REVISED APRIL 1996

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

CC

= – 50 µ

OH

OH

OL

I

I

I

CC

‡

∆I

CC

C

i

†

Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.

‡

This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

= – 24

OH

IOH = – 50 mA
IOH = – 75 mA

= 50 µ

OL

= 24

OL

IOL = 50 mA
IOL = 75 mA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
One input at 3.4 V ,

Other inputs at GND or V
VI = VCC or GND 5 V 2.6 pF

†
†

†
†

CC

4.5 V 4.4 4.49 4.4 4.4

5.5 V 5.4 5.49 5.4 5.4

4.5 V 3.86 3.7 3.76

5.5 V 4.86 4.7 4.76

5.5 V 3.85

5.5 V 3.85

4.5 V 0.001 0.1 0.1 0.1

5.5 V 0.001 0.1 0.1 0.1

4.5 V 0.36 0.5 0.44

5.5 V 0.36 0.5 0.44

5.5 V 1.65

5.5 V 1.65

5.5 V 0.6 1.6 1.5 mA

TA = 25°C SN54ACT86 SN74ACT86

MIN TYP MAX MIN MAX MIN MAX

switching characteristics over recommended operating free-air temperature range,

= 5 V " 0.5 V (unless otherwise noted) (see Figure 1)

V

CC

TA = 25°C SN54ACT86 SN74ACT86

MIN TYP MAX MIN MAX MIN MAX

1.5 8.5 9.5 1 10 1 10

1.5 7 9.5 1 10.5 1 10.5

t

PLH

t

PHL

FROM TO

(INPUT) (OUTPUT)

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

CpdPower dissipation capacitance CL = 50 pF, f = 1 MHz 25 pF

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT86, SN74ACT86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCAS534A – AUGUST 1995 – REVISED APRIL 1996

PARAMETER MEASUREMENT INFORMATION

S1TEST

t

PLH/tPHL

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.

Open

500 Ω

500 Ω

Figure 1. Load Circuit and Voltage Waveforms

S1

2 × V

Open

CC

Input

(see Note B)

In-Phase

Output

Out-of-Phase

Output

1.5 V

t

PLH

50% V

t

PHL

50% V

VOLTAGE WAVEFORMS

CC

CC

1.5 V

t

PHL

50% V

t

PLH

50% V

CC

CC

3 V

0 V

V

V

V

V

OH

OL

OH

OL

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5

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