Datasheet SN74ACT7814-20DL, SN74ACT7814-20DLR, SN74ACT7814-25DL, SN74ACT7814-25DLR, SN74ACT7814-40DL Datasheet (Texas Instruments)
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SN74ACT7814
64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209C – APRIL 1992 – REVISED APRIL 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
Load Clock and Unload Clock Can Be
Asynchronous or Coincident
D
64 Words by 18 Bits
D
Low-Power Advanced CMOS Technology
D
Full, Empty, and Half-Full Flags
D
Programmable Almost-Full/Almost-Empty
Flag
D
Fast Access Times of 15 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
D
Data Rates up to 50 MHz
D
3-State Outputs
D
Pin-to-Pin Compatible With SN74ACT7804
and SN74ACT7806
D
Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing
description
A FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. The SN74ACT7814 is a
64-word by 18-bit FIFO for high speed and fast
access times. It processes data at rates up to
50 MHz and access times of 15 ns in a bit-parallel
format.
Data is written into memory on a low-to-high
transition at the load clock (LDCK) input and is
read out on a low-to-high transition at the unload
clock (UNCK) input. The memory is full when the
number of words clocked in exceeds the number
of words clocked out by 64. When the memory is
full, LDCK signals have no effect on the data
residing in memory. When the memory is empty,
UNCK signals have no effect.
Status of the FIFO memory is monitored by the full (FULL
), empty (EMPTY), half-full (HF), and
almost-full/almost-empty (AF/AE) flags. The FULL
output is low when the memory is full and high when the
memory is not full. The EMPTY
output is low when the memory is empty and high when it is not empty . The HF
output is high when the FIFO contains 32 or more words and is low when it contains 31 or fewer words. The
AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are
used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN
)
is low. The AF/AE flag is high when the FIFO contains X or fewer words or (64 – Y) or more words. The AF/AE
flag is low when the FIFO contains between (X + 1) and (63 – Y) words.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
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24
25
26
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28
56
55
54
53
52
51
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49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RESET
D17
D16
D15
D14
D13
D12
D11
D10
V
CC
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HF
PEN
AF/AE
LDCK
NC
NC
FULL
OE
Q17
Q16
Q15
GND
Q14
V
CC
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
V
CC
Q4
Q3
Q2
GND
Q1
Q0
UNCK
NC
NC
EMPTY
DL PACKAGE
(TOP VIEW)
SN74ACT7814
64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209C – APRIL 1992 – REVISED APRIL 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
A low level on the reset (RESET) input resets the internal stack pointers and sets FULL high, HF low, and
EMPTY
low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up.
The first word loaded into empty memory causes EMPTY
to go high and the data to appear on the Q outputs.
It is important to note that the first word does not have to be unloaded. The data outputs are noninverting with
respect to the data inputs and are in the high-impedance state when the output-enable (OE
) input is high.
The SN74ACT7814 is characterized for operation from 0°C to 70°C.
logic symbol
†
0
21
D0
20
D1
19
D2
18
D3
17
D4
16
D5
15
D6
14
D7
12
D8
Q0
33
0
Q1
34
Q2
36
Q3
37
Q4
38
28
FULL
HF
22
HALF-FULL
AF/AE
24
ALMOST FULL/EMPTY
29
EMPTY
Q5
40
Q6
41
Q7
42
Q8
43
Data
1
11
D9
9
D10
8
D11
7
D12
6
D13
5
D14
4
D15
3
D16
17
2
D17
Q9
45
Q10
46
Q11
47
Q12
48
Q13
49
Q14
51
Q15
53
Q16
54
Q17
55
17
RESET
OE
PEN
RESET
1
25
LDCK
LDCK
Data
PROGRAM ENABLE
23
EN1
56
32
UNCK
UNCK
Φ
FIFO 64 × 18
SN74ACT7814
EMPTY
FULL
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN74ACT7814
64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209C – APRIL 1992 – REVISED APRIL 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Q0–Q17
AF/AE
HF
OE
D0–D17
UNCK
LDCK
RESET
PEN
EMPTY
FULL
Status-
Flag
Logic
Read
Pointer
Reset
Logic
Location 1
Location 2
Location 63
Location 64
64 × 18 SRAM
Write
Pointer
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
AF/AE 24 O
Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value
of 8 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when
memory contains X or fewer words or (64 – Y) or more words. AF/AE is high after reset.
D0–D17
2–9, 11–12,
14–21
I 18-bit data input port
EMPTY
29 O
Empty flag. EMPTY is high when the FIFO memory is not empty; EMPTY is low when the FIFO memory
is empty or upon assertion of RESET
.
FULL
28 O
Full flag. FULL is high when the FIFO memory is not full or upon assertion of RESET; FULL is low when
the FIFO memory is full.
HF 22 O Half-full flag. HF is high when the FIFO memory contains 32 or more words. HF is low after reset.
LDCK 25 I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state.
PEN 23 I
Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D4
is latched as an AF/AE offset value when PEN
is low and WRTCLK is high.
Q0–Q17
33–34, 36–38,
40–43, 45–49,
51, 53–55
O 18-bit data output port
RESET 1 I Reset. A low level on RESET resets the FIFO and drives FULL high and HF and EMPTY low.
UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.
SN74ACT7814
64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209C – APRIL 1992 – REVISED APRIL 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
offset values for AF/AE
The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset
value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. The
AF/AE flag is high when the FIFO contains X or fewer words or (64 – Y) or more words.
To program the offset values, PEN
can be brought low after reset only when LDCK is low. On the following
low-to-high transition of LDCK, the binary value on D0–D4 is stored as the almost-empty offset value (X) and
the almost-full offset value (Y). Holding PEN
low for another low-to-high transition of LDCK reprograms Y to the
binary value on D0–D4 at the time of the second LDCK low-to-high transition. Writes to the FIFO memory are
disabled while the offsets are programmed. A maximum value of 31 can be programmed for either X or Y (see
Figure 1). To use the default values of X = Y = 8, PEN
must be held high.
RESET
X and Y Y
PEN
D0–D4
EMPTY
Don’t Care
LDCK
Don’t Care
Figure 1. Programming X and Y Separately
SN74ACT7814
64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209C – APRIL 1992 – REVISED APRIL 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ÏÏ
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ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
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ÏÏ
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W64
FULL
EMPTY
D0–D17
RESET
PEN
Q0–Q17
AF/AE
W2 W33 W34
HF
OE
LDCK
UNCK
W1 W2 W32
W63 W64W1
Define the AF/AE Flag Using
the Default Value of X and Y
Don’t Care
(64–Y)
W
(X+1)
W
1
0
1
0
(Y+1)W(Y+2)
W
(64–X)W(65–X)
W
Figure 2. Write, Read, and Flag Timing Reference
Figure 2
SN74ACT7814
64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209C – APRIL 1992 – REVISED APRIL 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to a disabled 3-state output –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 1) 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
’ACT7814-20 ’ACT7814-25 ’ACT7814-40
MIN MAX MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 2 V
V
IL
Low-level input voltage 0.8 0.8 0.8 V
I
OH
High-level output current Q outputs, flags –8 –8 –8 mA
p
Q outputs 16 16 16
IOLLow-level output current
Flags 8 8 8
mA
T
A
Operating free-air temperature 0 70 0 70 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
V
OH
VCC = 4.5 V, IOH = –8 mA 2.4 V
Flags VCC = 4.5 V, IOL = 8 mA 0.5
V
OL
Q outputs VCC = 4.5 V, IOL = 16 mA 0.5
V
I
I
VCC = 5.5 V, VI =VCC or 0 ±5 µA
I
OZ
VCC = 5.5 V, VO =VCC or 0 ±5 µA
I
CC
VI = VCC – 0.2 V or 0 400 µA
∆I
CC
§
VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1 mA
C
i
VI = 0, f = 1 MHz 4 pF
C
o
VO = 0, f = 1 MHz 8 pF
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
This is the supply current for each input that is at one of the specified TTL voltage levels rather 0 V or VCC.
SN74ACT7814
64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209C – APRIL 1992 – REVISED APRIL 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating conditions (see Figures 1 through 3)
’ACT7814-20 ’ACT7814-25 ’ACT7814-40
MIN MAX MIN MAX MIN MAX
UNIT
f
clock
Clock frequency 50 40 25 MHz
LDCK high or low 7 8 12
UNCK high or low 7 8 12
twPulse duration
PEN low 7 8 12
ns
RESET low 10 10 12
D0–D17 before LDCK↑ 5 5 5
t
su
Setup time
PEN before LDCK↑ 5 5 5
ns
LDCK inactive before RESET high 5 6 6
D0–D17 after LDCK↑ 0 0 0
LDCK inactive after RESET high 5 6 6
thHold time
PEN low after LDCK↑ 3 3 3
ns
PEN high after LDCK↓ 0 0 0
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 3)
FROM TO
’ACT7814-20 ’ACT7814-25 ’ACT7814-40
PARAMETER
(INPUT) (OUTPUT)
MIN TYP†MAX MIN MAX MIN MAX
UNIT
f
max
LDCK or UNCK 50 40 25 MHz
LDCK↑
9 20 9 22 9 24
t
pd
UNCK↑
Any Q
6 11.5 15 6 18 6 20
ns
t
pd
‡
UNCK↑ Any Q 10.5 ns
t
PLH
LDCK↑
EMPTY
6 15 6 17 6 19 ns
UNCK↑
6 15 6 17 6 19
t
PHL
RESET low
EMPTY
4 16 4 18 4 20
ns
PHL
LDCK↑
FULL
6 15 6 17 6 19
UNCK↑
6 15 6 17 6 19
t
PLH
RESET low
FULL
4 18 4 20 4 22
ns
LDCK↑
7 18 7 20 7 22
t
pd
UNCK↑
AF/AE
7 18 7 20 7 22
ns
RESET low AF/AE 2 10 2 12 2 14
t
PLH
LDCK↑ HF 5 18 5 20 5 22
ns
UNCK↑
7 18 7 20 7 22
t
PHL
RESET low
HF
3 12 3 14 3 16
ns
t
en
OE
Any Q 2 9 2 10 2 11 ns
t
dis
OE
Any Q 2 10 2 11 2 12 ns
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
This parameter is measured at CL = 30 pF (see Figure 4).
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, f = 5 MHz 53 pF
SN74ACT7814
64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209C – APRIL 1992 – REVISED APRIL 1998
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
OH
V
OL
t
h
t
PLH
t
PHL
Output
Control
Output
Waveform 1
S1 at 7 V
Output
Waveform 2
S1 at Open
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
1.5 V 1.5 V
3 V
0 V
1.5 V 1.5 V
V
OH
V
OL
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
1.5 V
3 V
0 V
1.5 V 1.5 V
0 V
3 V
0 V
1.5 V 1.5 V
t
w
Input
3 V
3 V
≈ 3.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
S1
500 Ω
LOAD CIRCUIT
500 Ω
7 V
From Output
Under Test
Test
Point
NOTE A: CL includes probe and jig capacitance.
CL = 50 pF
(see Note A)
t
su
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
Open
Closed
Open
Closed
Open
Open
PARAMETER S1
t
en
t
dis
t
pd
Figure 3. Load Circuit and Voltage Waveforms
SN74ACT7814
64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209C – APRIL 1992 – REVISED APRIL 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 4
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
50 100 200 250150 300
pd
CL – Load Capacitance – pF
t
VCC = 5 V
TA = 25°C
RL = 500 Ω
0
typ + 8
typ + 6
typ + 4
typ + 2
typ
typ – 2
– Propagation Delay Time – ns
Figure 5
60
20
160
0
010203040
– Supply Current – mA
120
80
140
SUPPLY CURRENT
vs
CLOCK FREQUENCY
200
50 60 70
180
100
40
VCC = 5 V
VCC = 4.5 V
f
clock
– Clock Frequency – MHz
CC(f)
I
VCC = 5.5 V
TA = 75°C
CL = 0 pF
SN74ACT7814
64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209C – APRIL 1992 – REVISED APRIL 1998
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Q0–Q17
D18–D35
D0–D17
Q18–Q35
Q0–Q17
LDCK
UNCKLDCK
FULL
EMPTY
FULL
EMPTY
SN74ACT7814
FULL
EMPTY
LDCK
UNCK
SN74ACT7814
UNCK
D0–D17
D0–D17
Q0–Q17
OE
OE
OE
Figure 6. Word-Width Expansion: 64 × 36 Bits
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Copyright 1999, Texas Instruments Incorporated
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